Commit 411ad638 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards 



In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.

We don't need to set the CFF bit as selective update configuration in
PSR2_MAN_TRL_CTL is not overwritten anymore. I.e. we have valid
configuration in PSR2_MAN_TRK_CTL and in plane SEL_FETCH_* registers when
SFF bit gets cleared by the HW in case something triggers "frame change"
event after SFF bit is cleared.

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-6-jouni.hogander@intel.com
parent 3b5bf853

drivers/gpu/drm/i915/display/intel_psr.c

+15 −7
Original line number Diff line number Diff line
@@ -2359,7 +2359,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st 
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		lockdep_assert_held(&intel_dp->psr.lock);

		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)

		if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

			return;

		break;

	}
@@ -3130,6 +3130,10 @@ static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 
	if (!intel_dp->psr.psr2_sel_fetch_enabled)

		return;



	if (DISPLAY_VER(display) >= 20)

		intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),

			       LNL_SFF_CTL_SF_SINGLE_FULL_FRAME);

	else

		intel_de_write(display,

			       PSR2_MAN_TRK_CTL(display, cpu_transcoder),

			       man_trk_ctl_enable_bit_get(display) |
@@ -3239,6 +3243,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) 
		 * Still keep cff bit enabled as we don't have proper SU

		 * configuration in case update is sent for any reason after

		 * sff bit gets cleared by the HW on next vblank.

		 *

		 * NOTE: Setting cff bit is not needed for LunarLake onwards as

		 * we have own register for SFF bit and we are not overwriting

		 * existing SU configuration

		 */

		intel_psr_configure_full_frame_update(intel_dp);

	}