Unverified Commit 4152d33a authored by Sheetal's avatar Sheetal Committed by Mark Brown
Browse files

ASoC: tegra: AHUB: Add Tegra264 support 



Add Tegra264 AHUB support with following changes:
- Update Tegra264 IP instances: DMIC(2), DSPK(1), AMX(6), ADX(6), I2S(8).
- Update register offsets for Tegra264.
- Add soc_data for Tegra264 chip-specific variations.
- Increase channels_max to 32 for Tegra264 DAIs.

Signed-off-by: default avatarSheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-11-sheetal@nvidia.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7dc8299f

sound/soc/tegra/tegra210_ahub.c

+844 −4

File changed.

Preview size limit exceeded, changes collapsed.

sound/soc/tegra/tegra210_ahub.h

+47 −5
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * tegra210_ahub.h - TEGRA210 AHUB

 *

 * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2020-2025, NVIDIA CORPORATION.  All rights reserved.

 *

 */
@@ -28,7 +28,39 @@ 
#define TEGRA186_XBAR_REG_MASK_3			0x3f0f00ff

#define TEGRA186_XBAR_UPDATE_MAX_REG			4



#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)

/* Tegra264 specific */

#define TEGRA264_XBAR_PART1_RX				0x1000

#define TEGRA264_XBAR_PART2_RX				0x2000

#define TEGRA264_XBAR_PART3_RX				0x3000

#define TEGRA264_XBAR_PART4_RX				0x4000

#define TEGRA264_XBAR_PART0_ADX6_RX1			0x224

#define TEGRA264_XBAR_AUDIO_RX_COUNT			((TEGRA264_XBAR_PART0_ADX6_RX1 / 4) + 1)

#define TEGRA264_XBAR_REG_MASK_0			0xfffffff

#define TEGRA264_XBAR_REG_MASK_1			0x3f013f1f

#define TEGRA264_XBAR_REG_MASK_2			0xff3c0301

#define TEGRA264_XBAR_REG_MASK_3			0x3f00ffff

#define TEGRA264_XBAR_REG_MASK_4			0x7fff9f

#define TEGRA264_XBAR_UPDATE_MAX_REG			5



#define TEGRA264_AXBAR_ADMAIF_RX1			0x0

#define TEGRA264_AXBAR_SFC4_RX1				0x6c

#define TEGRA264_AXBAR_MIXER1_RX1			0x80

#define TEGRA264_AXBAR_MIXER1_RX10			0xa4

#define TEGRA264_AXBAR_DSPK1_RX1			0xc0

#define TEGRA264_AXBAR_OPE1_RX1				0x100

#define TEGRA264_AXBAR_MVC1_RX1				0x110

#define TEGRA264_AXBAR_MVC2_RX1				0x114

#define TEGRA264_AXBAR_AMX1_RX1				0x120

#define TEGRA264_AXBAR_AMX3_RX4				0x14c

#define TEGRA264_AXBAR_ADX1_RX1				0x160

#define TEGRA264_AXBAR_ASRC1_RX7			0x1a8

#define TEGRA264_AXBAR_ADMAIF_RX21			0x1d0

#define TEGRA264_AXBAR_ADX6_RX1				0x224



#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA264_XBAR_UPDATE_MAX_REG)



#define TEGRA264_MAX_REGISTER_ADDR (TEGRA264_XBAR_PART4_RX +		\

	(TEGRA210_XBAR_RX_STRIDE * (TEGRA264_XBAR_AUDIO_RX_COUNT - 1)))



#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +		\

	(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
@@ -76,6 +108,15 @@ 


#define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)



#define MUX_ENUM_CTRL_DECL_264(ename, id)				\

	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\

				 tegra264_ahub_mux_texts,		\

				 tegra264_ahub_mux_values);		\

	static const struct snd_kcontrol_new ename##_control =		\

		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\

				  tegra_ahub_get_value_enum,		\

				  tegra_ahub_put_value_enum)



#define WIDGETS(sname, ename)						     \

	SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0),  \

	SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
@@ -92,7 +133,7 @@ 
		.playback = {						\

			.stream_name = #sname " XBAR-Playback",		\

			.channels_min = 1,				\

			.channels_max = 16,				\

			.channels_max = 32,				\

			.rates = SNDRV_PCM_RATE_8000_192000,		\

			.formats = SNDRV_PCM_FMTBIT_S8 |		\

				SNDRV_PCM_FMTBIT_S16_LE |		\
@@ -102,7 +143,7 @@ 
		.capture = {						\

			.stream_name = #sname " XBAR-Capture",		\

			.channels_min = 1,				\

			.channels_max = 16,				\

			.channels_max = 32,				\

			.rates = SNDRV_PCM_RATE_8000_192000,		\

			.formats = SNDRV_PCM_FMTBIT_S8 |		\

				SNDRV_PCM_FMTBIT_S16_LE |		\
@@ -115,9 +156,10 @@ struct tegra_ahub_soc_data { 
	const struct regmap_config *regmap_config;

	const struct snd_soc_component_driver *cmpnt_drv;

	struct snd_soc_dai_driver *dai_drv;

	unsigned int mask[4];

	unsigned int mask[TEGRA_XBAR_UPDATE_MAX_REG];

	unsigned int reg_count;

	unsigned int num_dais;

	unsigned int xbar_part_size;

};



struct tegra_ahub {