Commit 4157c756 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/cdclk: Add intel_cdclk_min_cdclk_for_prefill() 



Introduce a helper to compute the min required cdclk frequency
for a given guardband size. This could be used to bump up the
cdclk in case the vblank is so small that the normally computed
minimum cdclk results in too slow a prefill.

Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-5-ville.syrjala@linux.intel.com
parent 2b4c2a5e

drivers/gpu/drm/i915/display/intel_cdclk.c

+12 −0
Original line number Diff line number Diff line
@@ -4120,3 +4120,15 @@ unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state 


	return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);

}



int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,

				      unsigned int prefill_lines_unadjusted,

				      unsigned int prefill_lines_available)

{

	struct intel_display *display = to_intel_display(crtc_state);

	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;

	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);



	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),

				ppc * prefill_lines_available);

}

drivers/gpu/drm/i915/display/intel_cdclk.h

+3 −0
Original line number Diff line number Diff line
@@ -72,5 +72,8 @@ void intel_cdclk_read_hw(struct intel_display *display); 


unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state);

unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);

int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,

				      unsigned int prefill_lines_unadjusted,

				      unsigned int prefill_lines_available);



#endif /* __INTEL_CDCLK_H__ */