Commit 41a2452c authored by Deepak Gupta's avatar Deepak Gupta Committed by Paul Walmsley
Browse files

riscv: add Zicfiss / Zicfilp extension CSR and bit definitions 



The Zicfiss and Zicfilp extensions are enabled via b3 and b2 in
*envcfg CSRs.  menvcfg controls enabling for S/HS mode.  henvcfg
controls enabling for VS.  senvcfg controls enabling for U/VU mode.

The Zicfilp extension extends *status CSRs to hold an 'expected
landing pad' bit.  A trap or interrupt can occur between an indirect
jmp/call and target instruction.  The 'expected landing pad' bit from
the CPU is recorded into the xstatus CSR so that when the supervisor
performs xret, the 'expected landing pad' state of the CPU can be
restored.

Zicfiss adds one new CSR, CSR_SSP, which contains the current shadow
stack pointer.

Signed-off-by: default avatarDeepak Gupta <debug@rivosinc.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6
Tested-by: default avatarValentin Haudiquet <valentin.haudiquet@canonical.com>
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-4-b55691eacf4f@rivosinc.com


[pjw@kernel.org: grouped CSR_SSP macro with the other CSR macros; clarified patch description]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent df117085

arch/riscv/include/asm/csr.h

+14 −0
Original line number Diff line number Diff line
@@ -18,6 +18,15 @@ 
#define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */

#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */



/* zicfilp landing pad status bit */

#define SR_SPELP	_AC(0x00800000, UL)

#define SR_MPELP	_AC(0x020000000000, UL)

#ifdef CONFIG_RISCV_M_MODE

#define SR_ELP		SR_MPELP

#else

#define SR_ELP		SR_SPELP

#endif



#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */

#define SR_FS_OFF	_AC(0x00000000, UL)

#define SR_FS_INITIAL	_AC(0x00002000, UL)
@@ -212,6 +221,8 @@ 
#define ENVCFG_PMM_PMLEN_16		(_AC(0x3, ULL) << 32)

#define ENVCFG_CBZE			(_AC(1, UL) << 7)

#define ENVCFG_CBCFE			(_AC(1, UL) << 6)

#define ENVCFG_LPE			(_AC(1, UL) << 2)

#define ENVCFG_SSE			(_AC(1, UL) << 3)

#define ENVCFG_CBIE_SHIFT		4

#define ENVCFG_CBIE			(_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)

#define ENVCFG_CBIE_ILL			_AC(0x0, UL)
@@ -321,6 +332,9 @@ 
#define CSR_STIMECMP		0x14D

#define CSR_STIMECMPH		0x15D



/* zicfiss user mode csr.  CSR_SSP holds current shadow stack pointer */

#define CSR_SSP			0x011



/* xtheadvector symbolic CSR names */

#define CSR_VXSAT		0x9

#define CSR_VXRM		0xa