Commit 420c6a6f authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Rodrigo Vivi
Browse files

drm/xe: fix HuC FW ordering for DG1 

The firmware definitions must be ordered based on platform, from newer
to older, which means that the DG1 FW must come before the ADL one.

Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8699


Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20230627222856.3165647-1-daniele.ceraolospurio@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 807e7cee

drivers/gpu/drm/xe/xe_uc_fw.c

+1 −1
Original line number Diff line number Diff line
@@ -111,9 +111,9 @@ struct fw_blobs_by_type { 
	fw_def(TIGERLAKE,	major_ver(i915,	guc,	tgl,	70, 5))



#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver)				\

	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\

	fw_def(ALDERLAKE_P,	no_ver(i915,	huc,	tgl))			\

	fw_def(ALDERLAKE_S,	no_ver(i915,	huc,	tgl))			\

	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\

	fw_def(ROCKETLAKE,	no_ver(i915,	huc,	tgl))			\

	fw_def(TIGERLAKE,	no_ver(i915,	huc,	tgl))