Commit 424421a7 authored by Qing Zhang's avatar Qing Zhang Committed by Huacai Chen
Browse files

LoongArch: ptrace: Add hardware single step support 



Use the generic ptrace_resume code for PTRACE_SYSCALL, PTRACE_CONT,
PTRACE_KILL and PTRACE_SINGLESTEP handling. This implies defining
arch_has_single_step() and implementing the user_enable_single_step()
and user_disable_single_step() functions.

LoongArch cannot do hardware single-stepping per se, the hardware
single-stepping it is achieved by configuring the instruction fetch
watchpoints (FWPS) and specifies that the next instruction must trigger
the watch exception by setting the mask bit. In some scenarios
CSR.FWPS.Skip is used to ignore the next hit result, avoid endless
repeated triggering of the same watchpoint without canceling it.

Signed-off-by: default avatarQing Zhang <zhangqing@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 356bd6f2

arch/loongarch/include/asm/inst.h

+38 −0
Original line number Diff line number Diff line
@@ -351,6 +351,44 @@ static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) 
		is_imm12_negative(ip->reg2i12_format.immediate);

}



static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs)

{

	switch (ip->reg0i26_format.opcode) {

	case b_op:

	case bl_op:

		if (ip->reg0i26_format.immediate_l == 0

		    && ip->reg0i26_format.immediate_h == 0)

			return true;

	}



	switch (ip->reg1i21_format.opcode) {

	case beqz_op:

	case bnez_op:

	case bceqz_op:

		if (ip->reg1i21_format.immediate_l == 0

		    && ip->reg1i21_format.immediate_h == 0)

			return true;

	}



	switch (ip->reg2i16_format.opcode) {

	case beq_op:

	case bne_op:

	case blt_op:

	case bge_op:

	case bltu_op:

	case bgeu_op:

		if (ip->reg2i16_format.immediate == 0)

			return true;

		break;

	case jirl_op:

		if (regs->regs[ip->reg2i16_format.rj] +

		    ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)

			return true;

	}



	return false;

}



int larch_insn_read(void *addr, u32 *insnp);

int larch_insn_write(void *addr, u32 insn);

int larch_insn_patch_text(void *addr, u32 insn);

arch/loongarch/include/asm/loongarch.h

+3 −0
Original line number Diff line number Diff line
@@ -1055,6 +1055,9 @@ static __always_inline void iocsr_write64(u64 val, u32 reg) 
#define LOONGARCH_CSR_DERA		0x501	/* debug era */

#define LOONGARCH_CSR_DESAVE		0x502	/* debug save */



#define CSR_FWPC_SKIP_SHIFT		16

#define CSR_FWPC_SKIP			(_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT)



/*

 * CSR_ECFG IM

 */

arch/loongarch/include/asm/processor.h

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ struct thread_struct { 
	/* Other stuff associated with the thread. */

	unsigned long trap_nr;

	unsigned long error_code;

	unsigned long single_step; /* Used by PTRACE_SINGLESTEP */

	struct loongarch_vdso_info *vdso;



	/*

arch/loongarch/include/asm/ptrace.h

+4 −0
Original line number Diff line number Diff line
@@ -183,4 +183,8 @@ static inline void user_stack_pointer_set(struct pt_regs *regs, 
	regs->regs[3] = val;

}



#ifdef CONFIG_HAVE_HW_BREAKPOINT

#define arch_has_single_step()		(1)

#endif



#endif /* _ASM_PTRACE_H */

arch/loongarch/kernel/hw_breakpoint.c

+29 −4
Original line number Diff line number Diff line
@@ -153,6 +153,22 @@ void ptrace_hw_copy_thread(struct task_struct *tsk) 
 */

void flush_ptrace_hw_breakpoint(struct task_struct *tsk)

{

	int i;

	struct thread_struct *t = &tsk->thread;



	for (i = 0; i < LOONGARCH_MAX_BRP; i++) {

		if (t->hbp_break[i]) {

			unregister_hw_breakpoint(t->hbp_break[i]);

			t->hbp_break[i] = NULL;

		}

	}



	for (i = 0; i < LOONGARCH_MAX_WRP; i++) {

		if (t->hbp_watch[i]) {

			unregister_hw_breakpoint(t->hbp_watch[i]);

			t->hbp_watch[i] = NULL;

		}

	}

}



static int hw_breakpoint_control(struct perf_event *bp,
@@ -501,13 +517,22 @@ arch_initcall(arch_hw_breakpoint_init); 


void hw_breakpoint_thread_switch(struct task_struct *next)

{

	u64 addr, mask;

	struct pt_regs *regs = task_pt_regs(next);



	if (test_tsk_thread_flag(next, TIF_SINGLESTEP)) {

		addr = read_wb_reg(CSR_CFG_ADDR, 0, 0);

		mask = read_wb_reg(CSR_CFG_MASK, 0, 0);

		if (!((regs->csr_era ^ addr) & ~mask))

			csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);

		regs->csr_prmd |= CSR_PRMD_PWE;

	} else {

		/* Update breakpoints */

		update_bp_registers(regs, 1, 0);

		/* Update watchpoints */

		update_bp_registers(regs, 1, 1);

	}

}



void hw_breakpoint_pmu_read(struct perf_event *bp)

{