Commit 425b8481 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.15-2025-02-21' of... 

Merge tag 'amd-drm-next-6.15-2025-02-21' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.15-2025-02-21:

amdgpu:
- Add OEM i2c support for RGB lights, etc.
- Add support for GC 11.5.3
- Add support for GC 11.5.2
- Add support for SDMA 6.1.3
- Add support for NBIO 7.11.2
- Add support for NBIO 7.9.1
- Add support for MMHUB 3.3.2
- Add support for MMHUB 1.8.1
- Add support for SMU 14.0.5
- Add support for SMUIO 13.0.11
- Add support for PSP 14.0.5
- Add support for UMC 12.5.0
- Add support for DCN 3.6.0
- JPEG 4.0.3 updates
- Add dynamic workload profile switching for GC 10-12
- support larger vbios sizes
- GC 9.5.0 updates
- SMU 13.0.12 updates
- SMU 13.0.6 updates
- IP discovery updates
- GC 10 queue reset updates
- DCN 4.0.1 updates
- UHBR link rate fixes
- Aborted suspend fix
- Mark gttsize parameter as deprecated
- GC 10 cleaner shader updates
- PSR-SU fixes
- Clean up PM4 headers
- Cursor fixes
- Enable devcoredump for JPEG
- Misc cleanups
- Runpm cleanups
- MES updates
- GC 9 gfxoff fixes
- Vbios fetching cleanups
- Documentation updates
- Update secondary plane handling
- DML2 updates
- SDMA fixes for MI
- Cleaner shader fixes for GC 11/12
- ACA updates
- Initial JPEG queue reset support
- RAS updates
- Initial RAS CPER support
- DCN/DCE panic screen handling cleanup
- BT2020 fixes
- SR-IOV fixes

amdkfd:
- synchronize pasid values between KGD and KFD
- Misc cleanups
- Improve GTT/VRAM handling for APUs
- Topology updates
- Fix user queue validation on GC 7/8

UAPI:
- Enable "Broadcast RGB" drm property
- Add INFO IOCTL query for virtualization mode
  Proposed userspace:
  https://github.com/ROCm/amdsmi/commit/e663bed7d6b3df79f5959e73981749b1f22ec698

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250221213651.4176031-1-alexander.deucher@amd.com


Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parents fb51bf02 3521276a

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -65,7 +65,8 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ 
	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o \

	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \

	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o

	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \

	amdgpu_cper.o



amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+11 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
#include "amdgpu_mca.h"

#include "amdgpu_aca.h"

#include "amdgpu_ras.h"

#include "amdgpu_cper.h"

#include "amdgpu_xcp.h"

#include "amdgpu_seq64.h"

#include "amdgpu_reg_state.h"
@@ -415,6 +416,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev); 
bool amdgpu_read_bios(struct amdgpu_device *adev);

bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,

				     u8 *bios, u32 length_bytes);

void amdgpu_bios_release(struct amdgpu_device *adev);

/*

 * Clocks

 */
@@ -1090,6 +1092,9 @@ struct amdgpu_device { 
	/* ACA */

	struct amdgpu_aca		aca;



	/* CPER */

	struct amdgpu_cper		cper;



	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];

	uint32_t		        harvest_ip_mask;

	int				num_ip_blocks;
@@ -1149,6 +1154,7 @@ struct amdgpu_device { 
	struct ratelimit_state		throttling_logging_rs;

	uint32_t                        ras_hw_enabled;

	uint32_t                        ras_enabled;

	bool                            ras_default_ecc_enabled;



	bool                            no_hw_access;

	struct pci_saved_state          *pci_state;
@@ -1192,6 +1198,11 @@ struct amdgpu_device { 
	struct mutex                    enforce_isolation_mutex;



	struct amdgpu_init_level *init_lvl;



	/* This flag is used to determine how VRAM allocations are handled for APUs

	 * in KFD: VRAM or GTT.

	 */

	bool                            apu_prefer_gtt;

};



static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c

+34 −12
Original line number Diff line number Diff line
@@ -30,16 +30,6 @@ 


typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);



struct aca_banks {

	int nr_banks;

	struct list_head list;

};



struct aca_hwip {

	int hwid;

	int mcatype;

};



static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = {

	ACA_BANK_HWID(SMU,	0x01,	0x01),

	ACA_BANK_HWID(PCS_XGMI, 0x50,	0x00),
@@ -111,7 +101,7 @@ static struct aca_regs_dump { 
	{"STATUS",		ACA_REG_IDX_STATUS},

	{"ADDR",		ACA_REG_IDX_ADDR},

	{"MISC",		ACA_REG_IDX_MISC0},

	{"CONFIG",		ACA_REG_IDX_CONFG},

	{"CONFIG",		ACA_REG_IDX_CONFIG},

	{"IPID",		ACA_REG_IDX_IPID},

	{"SYND",		ACA_REG_IDX_SYND},

	{"DESTAT",		ACA_REG_IDX_DESTAT},
@@ -168,7 +158,7 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_ 
		if (ret)

			return ret;



		bank.type = type;

		bank.smu_err_type = type;



		aca_smu_bank_dump(adev, i, count, &bank, qctx);
@@ -394,6 +384,36 @@ static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type 
	return ret;

}



static void aca_banks_generate_cper(struct amdgpu_device *adev,

				    enum aca_smu_type type,

				    struct aca_banks *banks,

				    int count)

{

	struct aca_bank_node *node;

	struct aca_bank *bank;



	if (!banks || !count) {

		dev_warn(adev->dev, "fail to generate cper records\n");

		return;

	}



	/* UEs must be encoded into separate CPER entries */

	if (type == ACA_SMU_TYPE_UE) {

		list_for_each_entry(node, &banks->list, node) {

			bank = &node->bank;

			if (amdgpu_cper_generate_ue_record(adev, bank))

				dev_warn(adev->dev, "fail to generate ue cper records\n");

		}

	} else {

		/*

		 * SMU_TYPE_CE banks are combined into 1 CPER entries,

		 * they could be CEs or DEs or both

		 */

		if (amdgpu_cper_generate_ce_records(adev, banks, count))

			dev_warn(adev->dev, "fail to generate ce cper records\n");

	}

}



static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,

			    bank_handler_t handler, struct ras_query_context *qctx, void *data)

{
@@ -431,6 +451,8 @@ static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type, 
	if (ret)

		goto err_release_banks;



	aca_banks_generate_cper(adev, type, &banks, count);



err_release_banks:

	aca_banks_release(&banks);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

+14 −2
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ enum aca_reg_idx { 
	ACA_REG_IDX_STATUS		= 1,

	ACA_REG_IDX_ADDR		= 2,

	ACA_REG_IDX_MISC0		= 3,

	ACA_REG_IDX_CONFG		= 4,

	ACA_REG_IDX_CONFIG		= 4,

	ACA_REG_IDX_IPID		= 5,

	ACA_REG_IDX_SYND		= 6,

	ACA_REG_IDX_DESTAT		= 8,
@@ -108,13 +108,20 @@ enum aca_error_type { 
};



enum aca_smu_type {

	ACA_SMU_TYPE_INVALID = -1,

	ACA_SMU_TYPE_UE = 0,

	ACA_SMU_TYPE_CE,

	ACA_SMU_TYPE_COUNT,

};



struct aca_hwip {

	int hwid;

	int mcatype;

};



struct aca_bank {

	enum aca_smu_type type;

	enum aca_error_type aca_err_type;

	enum aca_smu_type smu_err_type;

	u64 regs[ACA_MAX_REGS_COUNT];

};
@@ -123,6 +130,11 @@ struct aca_bank_node { 
	struct list_head node;

};



struct aca_banks {

	int nr_banks;

	struct list_head list;

};



struct aca_bank_info {

	int die_id;

	int socket_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+2 −2
Original line number Diff line number Diff line
@@ -459,7 +459,7 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 
		else

			mem_info->local_mem_size_private =

					KFD_XCP_MEMORY_SIZE(adev, xcp->id);

	} else if (adev->flags & AMD_IS_APU) {

	} else if (adev->apu_prefer_gtt) {

		mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT);

		mem_info->local_mem_size_private = 0;

	} else {
@@ -818,7 +818,7 @@ u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 
		}

		do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);

		return ALIGN_DOWN(tmp, PAGE_SIZE);

	} else if (adev->flags & AMD_IS_APU) {

	} else if (adev->apu_prefer_gtt) {

		return (ttm_tt_pages_limit() << PAGE_SHIFT);

	} else {

		return adev->gmc.real_vram_size;