Commit 42a0305a authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-6.17-1' of... 

Merge tag 'kvmarm-fixes-6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 changes for 6.17, take #2

 - Correctly handle 'invariant' system registers for protected VMs

 - Improved handling of VNCR data aborts, including external aborts

 - Fixes for handling of FEAT_RAS for NV guests, providing a sane
   fault context during SEA injection and preventing the use of
   RASv1p1 fault injection hardware

 - Ensure that page table destruction when a VM is destroyed gives an
   opportunity to reschedule

 - Large fix to KVM's infrastructure for managing guest context loaded
   on the CPU, addressing issues where the output of AT emulation
   doesn't get reflected to the guest

 - Fix AT S12 emulation to actually perform stage-2 translation when
   necessary

 - Avoid attempting vLPI irqbypass when GICv4 has been explicitly
   disabled for a VM

 - Minor KVM + selftest fixes
parents 085e899a ee372e64

arch/arm64/include/asm/kvm_host.h

+2 −109
Original line number Diff line number Diff line
@@ -1160,115 +1160,8 @@ u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 
		__v;							\

	})



u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);

void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);



static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)

{

	/*

	 * *** VHE ONLY ***

	 *

	 * System registers listed in the switch are not saved on every

	 * exit from the guest but are only saved on vcpu_put.

	 *

	 * SYSREGS_ON_CPU *MUST* be checked before using this helper.

	 *

	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but

	 * should never be listed below, because the guest cannot modify its

	 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's

	 * thread when emulating cross-VCPU communication.

	 */

	if (!has_vhe())

		return false;



	switch (reg) {

	case SCTLR_EL1:		*val = read_sysreg_s(SYS_SCTLR_EL12);	break;

	case CPACR_EL1:		*val = read_sysreg_s(SYS_CPACR_EL12);	break;

	case TTBR0_EL1:		*val = read_sysreg_s(SYS_TTBR0_EL12);	break;

	case TTBR1_EL1:		*val = read_sysreg_s(SYS_TTBR1_EL12);	break;

	case TCR_EL1:		*val = read_sysreg_s(SYS_TCR_EL12);	break;

	case TCR2_EL1:		*val = read_sysreg_s(SYS_TCR2_EL12);	break;

	case PIR_EL1:		*val = read_sysreg_s(SYS_PIR_EL12);	break;

	case PIRE0_EL1:		*val = read_sysreg_s(SYS_PIRE0_EL12);	break;

	case POR_EL1:		*val = read_sysreg_s(SYS_POR_EL12);	break;

	case ESR_EL1:		*val = read_sysreg_s(SYS_ESR_EL12);	break;

	case AFSR0_EL1:		*val = read_sysreg_s(SYS_AFSR0_EL12);	break;

	case AFSR1_EL1:		*val = read_sysreg_s(SYS_AFSR1_EL12);	break;

	case FAR_EL1:		*val = read_sysreg_s(SYS_FAR_EL12);	break;

	case MAIR_EL1:		*val = read_sysreg_s(SYS_MAIR_EL12);	break;

	case VBAR_EL1:		*val = read_sysreg_s(SYS_VBAR_EL12);	break;

	case CONTEXTIDR_EL1:	*val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;

	case TPIDR_EL0:		*val = read_sysreg_s(SYS_TPIDR_EL0);	break;

	case TPIDRRO_EL0:	*val = read_sysreg_s(SYS_TPIDRRO_EL0);	break;

	case TPIDR_EL1:		*val = read_sysreg_s(SYS_TPIDR_EL1);	break;

	case AMAIR_EL1:		*val = read_sysreg_s(SYS_AMAIR_EL12);	break;

	case CNTKCTL_EL1:	*val = read_sysreg_s(SYS_CNTKCTL_EL12);	break;

	case ELR_EL1:		*val = read_sysreg_s(SYS_ELR_EL12);	break;

	case SPSR_EL1:		*val = read_sysreg_s(SYS_SPSR_EL12);	break;

	case PAR_EL1:		*val = read_sysreg_par();		break;

	case DACR32_EL2:	*val = read_sysreg_s(SYS_DACR32_EL2);	break;

	case IFSR32_EL2:	*val = read_sysreg_s(SYS_IFSR32_EL2);	break;

	case DBGVCR32_EL2:	*val = read_sysreg_s(SYS_DBGVCR32_EL2);	break;

	case ZCR_EL1:		*val = read_sysreg_s(SYS_ZCR_EL12);	break;

	case SCTLR2_EL1:	*val = read_sysreg_s(SYS_SCTLR2_EL12);	break;

	default:		return false;

	}



	return true;

}



static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)

{

	/*

	 * *** VHE ONLY ***

	 *

	 * System registers listed in the switch are not restored on every

	 * entry to the guest but are only restored on vcpu_load.

	 *

	 * SYSREGS_ON_CPU *MUST* be checked before using this helper.

	 *

	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but

	 * should never be listed below, because the MPIDR should only be set

	 * once, before running the VCPU, and never changed later.

	 */

	if (!has_vhe())

		return false;



	switch (reg) {

	case SCTLR_EL1:		write_sysreg_s(val, SYS_SCTLR_EL12);	break;

	case CPACR_EL1:		write_sysreg_s(val, SYS_CPACR_EL12);	break;

	case TTBR0_EL1:		write_sysreg_s(val, SYS_TTBR0_EL12);	break;

	case TTBR1_EL1:		write_sysreg_s(val, SYS_TTBR1_EL12);	break;

	case TCR_EL1:		write_sysreg_s(val, SYS_TCR_EL12);	break;

	case TCR2_EL1:		write_sysreg_s(val, SYS_TCR2_EL12);	break;

	case PIR_EL1:		write_sysreg_s(val, SYS_PIR_EL12);	break;

	case PIRE0_EL1:		write_sysreg_s(val, SYS_PIRE0_EL12);	break;

	case POR_EL1:		write_sysreg_s(val, SYS_POR_EL12);	break;

	case ESR_EL1:		write_sysreg_s(val, SYS_ESR_EL12);	break;

	case AFSR0_EL1:		write_sysreg_s(val, SYS_AFSR0_EL12);	break;

	case AFSR1_EL1:		write_sysreg_s(val, SYS_AFSR1_EL12);	break;

	case FAR_EL1:		write_sysreg_s(val, SYS_FAR_EL12);	break;

	case MAIR_EL1:		write_sysreg_s(val, SYS_MAIR_EL12);	break;

	case VBAR_EL1:		write_sysreg_s(val, SYS_VBAR_EL12);	break;

	case CONTEXTIDR_EL1:	write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;

	case TPIDR_EL0:		write_sysreg_s(val, SYS_TPIDR_EL0);	break;

	case TPIDRRO_EL0:	write_sysreg_s(val, SYS_TPIDRRO_EL0);	break;

	case TPIDR_EL1:		write_sysreg_s(val, SYS_TPIDR_EL1);	break;

	case AMAIR_EL1:		write_sysreg_s(val, SYS_AMAIR_EL12);	break;

	case CNTKCTL_EL1:	write_sysreg_s(val, SYS_CNTKCTL_EL12);	break;

	case ELR_EL1:		write_sysreg_s(val, SYS_ELR_EL12);	break;

	case SPSR_EL1:		write_sysreg_s(val, SYS_SPSR_EL12);	break;

	case PAR_EL1:		write_sysreg_s(val, SYS_PAR_EL1);	break;

	case DACR32_EL2:	write_sysreg_s(val, SYS_DACR32_EL2);	break;

	case IFSR32_EL2:	write_sysreg_s(val, SYS_IFSR32_EL2);	break;

	case DBGVCR32_EL2:	write_sysreg_s(val, SYS_DBGVCR32_EL2);	break;

	case ZCR_EL1:		write_sysreg_s(val, SYS_ZCR_EL12);	break;

	case SCTLR2_EL1:	write_sysreg_s(val, SYS_SCTLR2_EL12);	break;

	default:		return false;

	}



	return true;

}

u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg);

void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg);



struct kvm_vm_stat {

	struct kvm_vm_stat_generic generic;

arch/arm64/include/asm/kvm_mmu.h

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu); 
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,

			  phys_addr_t pa, unsigned long size, bool writable);



int kvm_handle_guest_sea(struct kvm_vcpu *vcpu);

int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);



phys_addr_t kvm_mmu_get_httbr(void);

arch/arm64/include/asm/kvm_pgtable.h

+30 −0
Original line number Diff line number Diff line
@@ -355,6 +355,11 @@ static inline kvm_pte_t *kvm_dereference_pteref(struct kvm_pgtable_walker *walke 
	return pteref;

}



static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref)

{

	return pteref;

}



static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker)

{

	/*
@@ -384,6 +389,11 @@ static inline kvm_pte_t *kvm_dereference_pteref(struct kvm_pgtable_walker *walke 
	return rcu_dereference_check(pteref, !(walker->flags & KVM_PGTABLE_WALK_SHARED));

}



static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref)

{

	return rcu_dereference_raw(pteref);

}



static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker)

{

	if (walker->flags & KVM_PGTABLE_WALK_SHARED)
@@ -551,6 +561,26 @@ static inline int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2 
 */

void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);



/**

 * kvm_pgtable_stage2_destroy_range() - Destroy the unlinked range of addresses.

 * @pgt:	Page-table structure initialised by kvm_pgtable_stage2_init*().

 * @addr:      Intermediate physical address at which to place the mapping.

 * @size:      Size of the mapping.

 *

 * The page-table is assumed to be unreachable by any hardware walkers prior

 * to freeing and therefore no TLB invalidation is performed.

 */

void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,

					u64 addr, u64 size);



/**

 * kvm_pgtable_stage2_destroy_pgd() - Destroy the PGD of guest stage-2 page-table.

 * @pgt:       Page-table structure initialised by kvm_pgtable_stage2_init*().

 *

 * It is assumed that the rest of the page-table is freed before this operation.

 */

void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt);



/**

 * kvm_pgtable_stage2_free_unlinked() - Free an unlinked stage-2 paging structure.

 * @mm_ops:	Memory management callbacks.

arch/arm64/include/asm/kvm_pkvm.h

+3 −1
Original line number Diff line number Diff line
@@ -179,7 +179,9 @@ struct pkvm_mapping { 


int pkvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2_mmu *mmu,

			     struct kvm_pgtable_mm_ops *mm_ops);

void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);

void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,

					u64 addr, u64 size);

void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt);

int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys,

			    enum kvm_pgtable_prot prot, void *mc,

			    enum kvm_pgtable_walk_flags flags);

arch/arm64/include/asm/kvm_ras.h

deleted100644 → 0
+0 −25
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2018 - Arm Ltd */



#ifndef __ARM64_KVM_RAS_H__

#define __ARM64_KVM_RAS_H__



#include <linux/acpi.h>

#include <linux/errno.h>

#include <linux/types.h>



#include <asm/acpi.h>



/*

 * Was this synchronous external abort a RAS notification?

 * Returns '0' for errors handled by some RAS subsystem, or -ENOENT.

 */

static inline int kvm_handle_guest_sea(void)

{

	/* apei_claim_sea(NULL) expects to mask interrupts itself */

	lockdep_assert_irqs_enabled();



	return apei_claim_sea(NULL);

}



#endif /* __ARM64_KVM_RAS_H__ */