Unverified Commit 42ca4f0c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-7.1' of... 

Merge tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clock driver updates from Krzysztof Kozlowski:

 - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
   controllers on the SoC
 - ExynosAutov920: Add G3D (GPU) clock controller
 - Exynos850: Define missing clock for the APM mailbox

* tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: exynos850: Add APM-to-AP mailbox clock
  dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock
  clk: samsung: Use %pe format to simplify
  clk: samsung: pll: Fix possible truncation in a9fraco recalc rate
  clk: samsung: exynosautov920: add block G3D clock support
  dt-bindings: clock: exynosautov920: add G3D clock definitions
  clk: samsung: gs101: harmonise symbol names (clock arrays)
  clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC
  clk: samsung: Add clock PLL support for ARTPEC-9 SoC
  dt-bindings: clock: Add ARTPEC-9 clock controller
parents c3692998 e57c36bc

Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Axis ARTPEC-9 SoC clock controller



maintainers:

  - Jesper Nilsson <jesper.nilsson@axis.com>



description: |

  ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)

  units, generating clocks for different domains. Those CMU units are modeled

  as separate device tree nodes, and might depend on each other.

  The root clock in that root tree is an external clock: OSCCLK (25 MHz).

  This external clock must be defined as a fixed-rate clock in dts.



  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers, all other clocks of function blocks (other CMUs) are usually

  derived from CMU_CMU.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/axis,artpec9-clk.h' header.



properties:

  compatible:

    enum:

      - axis,artpec9-cmu-cmu

      - axis,artpec9-cmu-bus

      - axis,artpec9-cmu-core

      - axis,artpec9-cmu-cpucl

      - axis,artpec9-cmu-fsys0

      - axis,artpec9-cmu-fsys1

      - axis,artpec9-cmu-imem

      - axis,artpec9-cmu-peri



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



allOf:

  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-cmu



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)



        clock-names:

          items:

            - const: fin_pll



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-bus



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_BUS bus clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: bus



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-core



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CORE main clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: main



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-cpucl



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CPUCL switch clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: switch



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-fsys0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_FSYS0 bus clock (from CMU_CMU)

            - description: CMU_FSYS0 IP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: bus

            - const: ip



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-fsys1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_FSYS1 scan0 clock (from CMU_CMU)

            - description: CMU_FSYS1 scan1 clock (from CMU_CMU)

            - description: CMU_FSYS1 bus clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: scan0

            - const: scan1

            - const: bus



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-imem



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_IMEM ACLK clock (from CMU_CMU)

            - description: CMU_IMEM CA5 clock (from CMU_CMU)

            - description: CMU_IMEM JPEG clock (from CMU_CMU)

            - description: CMU_IMEM SSS clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: aclk

            - const: ca5

            - const: jpeg

            - const: sss



  - if:

      properties:

        compatible:

          const: axis,artpec9-cmu-peri



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_PERI IP clock (from CMU_CMU)

            - description: CMU_PERI DISP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: ip

            - const: disp



additionalProperties: false



examples:

  # Clock controller node for CMU_FSYS1

  - |

    #include <dt-bindings/clock/axis,artpec9-clk.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        cmu_fsys1: clock-controller@14c10000 {

            compatible = "axis,artpec9-cmu-fsys1";

            reg = <0x0 0x14c10000 0x0 0x4000>;

            #clock-cells = <1>;

            clocks = <&fin_pll>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,

                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;

            clock-names = "fin_pll", "scan0", "scan1", "bus";

        };

    };

...

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

+21 −0
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@@ -35,6 +35,7 @@ properties: 
      - samsung,exynosautov920-cmu-cpucl0

      - samsung,exynosautov920-cmu-cpucl1

      - samsung,exynosautov920-cmu-cpucl2

      - samsung,exynosautov920-cmu-g3d

      - samsung,exynosautov920-cmu-hsi0

      - samsung,exynosautov920-cmu-hsi1

      - samsung,exynosautov920-cmu-hsi2
@@ -287,6 +288,26 @@ allOf: 
            - const: oscclk

            - const: noc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov920-cmu-g3d



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_G3D SWITCH clock (from CMU_TOP)

            - description: CMU_G3D NOCP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: nocp



required:

  - compatible

  - "#clock-cells"

drivers/clk/samsung/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o 
obj-$(CONFIG_EXYNOS_5420_COMMON_CLK)	+= clk-exynos5420.o

obj-$(CONFIG_EXYNOS_5420_COMMON_CLK)	+= clk-exynos5-subcmu.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-artpec8.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-artpec9.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos5433.o

obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o

obj-$(CONFIG_EXYNOS_CLKOUT)	+= clk-exynos-clkout.o

drivers/clk/samsung/clk-artpec9.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/samsung/clk-exynos850.c

+6 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_TOP			(CLK_DOUT_CPUCL1_SWITCH + 1)

#define CLKS_NR_APM			(CLK_GOUT_SYSREG_APM_PCLK + 1)

#define CLKS_NR_APM			(CLK_GOUT_MAILBOX_APM_AP_PCLK + 1)

#define CLKS_NR_AUD			(CLK_GOUT_AUD_CMU_AUD_PCLK + 1)

#define CLKS_NR_CMGP			(CLK_GOUT_SYSREG_CMGP_PCLK + 1)

#define CLKS_NR_CPUCL0			(CLK_CLUSTER0_SCLK + 1)
@@ -604,6 +604,7 @@ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK		0x2028

#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK	0x2034

#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK	0x2038

#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK	0x2060

#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK		0x20bc

#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK		0x20c0
@@ -628,6 +629,7 @@ static const unsigned long apm_clk_regs[] __initconst = { 
	CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,

	CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,

	CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,

	CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK,

};



/* List of parent clocks for Muxes in CMU_APM */
@@ -698,6 +700,9 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 
	     CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),

	GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",

	     CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_MAILBOX_APM_AP_PCLK, "gout_mailbox_apm_ap_pclk",

	     "dout_apm_func",

	     CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK, 21, 0, 0),

};



static const struct samsung_cmu_info apm_cmu_info __initconst = {