Commit 430ad3f0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

alpha: remove LCA and APECS based machines 



APECS is the DECchip 21071x chipset for the EV4 and EV45 generation, while
LCA is the integrated I/O support on the corresponding low-cost alpha
machines of that generation.

All of these CPUs lack the BWX extension for byte and word access, so
drop the chipset support and all associated machines.

Acked-by: default avatarPaul E. McKenney <paulmck@kernel.org>
Acked-by: default avatarMatt Turner <mattst88@gmail.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent d2b1e353

arch/alpha/Kconfig

+5 −109
Original line number Diff line number Diff line
@@ -90,20 +90,12 @@ choice 
	  <http://www.alphalinux.org/>. In summary:



	  Alcor/Alpha-XLT     AS 600, AS 500, XL-300, XL-366

	  Alpha-XL            XL-233, XL-266

	  AlphaBook1          Alpha laptop

	  Avanti              AS 200, AS 205, AS 250, AS 255, AS 300, AS 400

	  Cabriolet           AlphaPC64, AlphaPCI64

	  DP264               DP264 / DS20 / ES40 / DS10 / DS10L

	  EB164               EB164 21164 evaluation board

	  EB64+               EB64+ 21064 evaluation board

	  EB66                EB66 21066 evaluation board

	  EB66+               EB66+ 21066 evaluation board

	  LX164               AlphaPC164-LX

	  Miata               Personal Workstation 433/500/600 a/au

	  Marvel              AlphaServer ES47 / ES80 / GS1280

	  Mikasa              AS 1000

	  Noname              AXPpci33, UDB (Multia)

	  Noritake            AS 1000A, AS 600A, AS 800

	  PC164               AlphaPC164

	  Rawhide             AS 1200, AS 4000, AS 4100
@@ -135,27 +127,6 @@ config ALPHA_ALCOR 
	  all the work required to support an external Bcache and to maintain

	  memory coherence when a PCI device DMAs into (or out of) memory.



config ALPHA_XL

	bool "Alpha-XL"

	help

	  XL-233 and XL-266-based Alpha systems.



config ALPHA_BOOK1

	bool "AlphaBook1"

	help

	  Dec AlphaBook1/Burns Alpha-based laptops.



config ALPHA_AVANTI_CH

	bool "Avanti"



config ALPHA_CABRIOLET

	bool "Cabriolet"

	help

	  Cabriolet AlphaPC64, AlphaPCI64 systems.  Derived from EB64+ but now

	  baby-AT with Flash boot ROM, no on-board SCSI or Ethernet. 3 ISA

	  slots, 4 PCI slots (one pair are on a shared slot), uses plug-in

	  Bcache SIMMs.  Requires power supply with 3.3V output.



config ALPHA_DP264

	bool "DP264"

	help
@@ -173,23 +144,6 @@ config ALPHA_EB164 
	  MOUSE (PS2 style), RTC/NVRAM.  Boot ROM is Flash.  PC-AT-sized

	  motherboard.  Requires power supply with 3.3V output.



config ALPHA_EB64P_CH

	bool "EB64+"



config ALPHA_EB66

	bool "EB66"

	help

	  A Digital DS group board.  Uses 21066 or 21066A.  I/O sub-system is

	  identical to EB64+.  Baby PC-AT size.  Runs from standard PC power

	  supply.  The EB66 schematic was published as a marketing poster

	  advertising the 21066 as "the first microprocessor in the world with

	  embedded PCI".



config ALPHA_EB66P

	bool "EB66+"

	help

	  Later variant of the EB66 board.



config ALPHA_EIGER

	bool "Eiger"

	help
@@ -224,9 +178,6 @@ config ALPHA_NAUTILUS 
	help

	  Alpha systems based on the AMD 751 & ALI 1543C chipsets.



config ALPHA_NONAME_CH

	bool "Noname"



config ALPHA_NORITAKE

	bool "Noritake"

	select HAVE_EISA
@@ -237,9 +188,6 @@ config ALPHA_NORITAKE 
config ALPHA_PC164

	bool "PC164"



config ALPHA_P2K

	bool "Platform2000"



config ALPHA_RAWHIDE

	bool "Rawhide"

	select HAVE_EISA
@@ -303,53 +251,16 @@ config ISA_DMA_API 
	bool

	default y



config ALPHA_NONAME

	bool

	depends on ALPHA_BOOK1 || ALPHA_NONAME_CH

	default y

	help

	  The AXPpci33 (aka NoName), is based on the EB66 (includes the Multia

	  UDB).  This design was produced by Digital's Technical OEM (TOEM)

	  group. It uses the 21066 processor running at 166MHz or 233MHz. It

	  is a baby-AT size, and runs from a standard PC power supply. It has

	  5 ISA slots and 3 PCI slots (one pair are a shared slot). There are

	  2 versions, with either PS/2 or large DIN connectors for the

	  keyboard.



config ALPHA_EV4

	bool

	depends on ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K

	default y



config ALPHA_LCA

	bool

	depends on ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K

	default y



config ALPHA_APECS

	bool

	depends on !ALPHA_PRIMO && (ALPHA_NORITAKE || ALPHA_MIKASA) || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL

	default y



config ALPHA_EB64P

	bool

	depends on ALPHA_CABRIOLET || ALPHA_EB64P_CH

	default y

	help

	  Uses 21064 or 21064A and APECs.  Has ISA and PCI expansion (3 ISA,

	  2 PCI, one pair are on a shared slot). Supports 36-bit DRAM SIMs.

	  ISA bus generated by Intel SaturnI/O PCI-ISA bridge. On-board SCSI

	  (NCR 810 on PCI) Ethernet (Digital 21040), KBD, MOUSE (PS2 style),

	  SuperI/O (2S, 1P, FD), RTC/NVRAM. Boot ROM is EPROM.  PC-AT size.

	  Runs from standard PC power supply.



config ALPHA_EV5

	bool

	default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR

	default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR



config ALPHA_CIA

	bool

	depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR

	depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR

	default y



config ALPHA_EV56
@@ -358,18 +269,12 @@ config ALPHA_EV56 


config ALPHA_EV56

	prompt "EV56 CPU (speed >= 333MHz)?"

	depends on ALPHA_NORITAKE || ALPHA_PRIMO

	depends on ALPHA_NORITAKE || ALPHA_MIKASA



config ALPHA_EV56

	prompt "EV56 CPU (speed >= 400MHz)?"

	depends on ALPHA_RAWHIDE



config ALPHA_PRIMO

	bool "EV5 CPU daughtercard (model 5/xxx)?"

	depends on ALPHA_NORITAKE || ALPHA_MIKASA

	help

	  Say Y if you have an AS 1000 5/xxx or an AS 1000A 5/xxx.



config ALPHA_T2

	bool

	depends on ALPHA_SABLE
@@ -416,15 +321,6 @@ config GENERIC_HWEIGHT 
	bool

	default y if !ALPHA_EV67



config ALPHA_AVANTI

	bool

	depends on ALPHA_XL || ALPHA_AVANTI_CH

	default y

	help

	  Avanti AS 200, AS 205, AS 250, AS 255, AS 300, and AS 400-based

	  Alphas. Info at

	  <http://www.unix-ag.org/Linux-Alpha/Architectures/Avanti.html>.



config ALPHA_BROKEN_IRQ_MASK

	bool

	depends on ALPHA_GENERIC || ALPHA_PC164
@@ -454,7 +350,7 @@ config ALPHA_QEMU 




config ALPHA_SRM

	bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME

	bool "Use SRM as bootloader" if ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS

	depends on TTY

	default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL

	help
@@ -518,7 +414,7 @@ config ARCH_SPARSEMEM_ENABLE 
config ALPHA_WTINT

	bool "Use WTINT" if ALPHA_SRM || ALPHA_GENERIC

	default y if ALPHA_QEMU

	default n if ALPHA_EV5 || ALPHA_EV56 || (ALPHA_EV4 && !ALPHA_LCA)

	default n if ALPHA_EV5 || ALPHA_EV56

	default n if !ALPHA_SRM && !ALPHA_GENERIC

	default y if SMP

	help

arch/alpha/include/asm/core_apecs.h

deleted100644 → 0
+0 −534
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ALPHA_APECS__H__

#define __ALPHA_APECS__H__



#include <linux/types.h>

#include <asm/compiler.h>



/*

 * APECS is the internal name for the 2107x chipset which provides

 * memory controller and PCI access for the 21064 chip based systems.

 *

 * This file is based on:

 *

 * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets

 * Data Sheet

 *

 * EC-N0648-72

 *

 *

 * david.rusling@reo.mts.dec.com Initial Version.

 *

 */



/*

   An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address

   that get passed through the PCI<->ISA bridge chip. So we've gotta use

   both windows to max out the physical memory we can DMA to. Sigh...



   If we try a window at 0 for 1GB as a work-around, we run into conflicts

   with ISA/PCI bus memory which can't be relocated, like VGA aperture and

   BIOS ROMs. So we must put the windows high enough to avoid these areas.



   We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,

   and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.

   Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually

   be used for that range (via virt_to_bus()).



   Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,

   to keep virt_to_bus() from returning an address in the first window, for

   a data area that goes beyond the 64Mb first DMA window.  Sigh...

   The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but

   we can't just use that here, because of header file looping... :-(



   Window 1 will be used for all DMA from the ISA bus; yes, that does

   limit what memory an ISA floppy or sound card or Ethernet can touch, but

   it's also a known limitation on other platforms as well. We use the

   same technique that is used on INTEL platforms with similar limitation:

   set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().

   We trust that any ISA bus device drivers will *always* ask for DMAable

   memory explicitly via kmalloc()/get_free_pages() flags arguments.



   Note that most PCI bus devices' drivers do *not* explicitly ask for

   DMAable memory; they count on being able to DMA to any memory they

   get from kmalloc()/get_free_pages(). They will also use window 1 for

   any physical memory accesses below 64Mb; the rest will be handled by

   window 2, maxing out at 1Gb of memory. I trust this is enough... :-)



   We hope that the area before the first window is large enough so that

   there will be no overlap at the top end (64Mb). We *must* locate the

   PCI cards' memory just below window 1, so that there's still the

   possibility of being able to access it via SPARSE space. This is

   important for cards such as the Matrox Millennium, whose Xserver

   wants to access memory-mapped registers in byte and short lengths.



   Note that the XL is treated differently from the AVANTI, even though

   for most other things they are identical. It didn't seem reasonable to

   make the AVANTI support pay for the limitations of the XL. It is true,

   however, that an XL kernel will run on an AVANTI without problems.



   %%% All of this should be obviated by the ability to route

   everything through the iommu.

*/



/*

 * 21071-DA Control and Status registers.

 * These are used for PCI memory access.

 */

#define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)

#define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)

#define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)

#define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)

#define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)

#define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)



#define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)

#define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)



#define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)

#define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)



#define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)

#define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)



#define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)

#define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)

#define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)



#define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)



#define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)

#define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)

#define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)

#define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)

#define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)

#define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)

#define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)

#define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)



#define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)

#define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)

#define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)

#define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)

#define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)

#define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)

#define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)

#define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)



#define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)





/*

 * 21071-CA Control and Status registers.

 * These are used to program memory timing,

 *  configure memory and initialise the B-Cache.

 */

#define APECS_MEM_GCR		        (IDENT_ADDR + 0x180000000UL)

#define APECS_MEM_EDSR		        (IDENT_ADDR + 0x180000040UL)

#define APECS_MEM_TAR  		        (IDENT_ADDR + 0x180000060UL)

#define APECS_MEM_ELAR		        (IDENT_ADDR + 0x180000080UL)

#define APECS_MEM_EHAR  		(IDENT_ADDR + 0x1800000a0UL)

#define APECS_MEM_SFT_RST		(IDENT_ADDR + 0x1800000c0UL)

#define APECS_MEM_LDxLAR 		(IDENT_ADDR + 0x1800000e0UL)

#define APECS_MEM_LDxHAR 		(IDENT_ADDR + 0x180000100UL)

#define APECS_MEM_GTR    		(IDENT_ADDR + 0x180000200UL)

#define APECS_MEM_RTR    		(IDENT_ADDR + 0x180000220UL)

#define APECS_MEM_VFPR   		(IDENT_ADDR + 0x180000240UL)

#define APECS_MEM_PDLDR  		(IDENT_ADDR + 0x180000260UL)

#define APECS_MEM_PDhDR  		(IDENT_ADDR + 0x180000280UL)



/* Bank x Base Address Register */

#define APECS_MEM_B0BAR  		(IDENT_ADDR + 0x180000800UL)

#define APECS_MEM_B1BAR  		(IDENT_ADDR + 0x180000820UL)

#define APECS_MEM_B2BAR  		(IDENT_ADDR + 0x180000840UL)

#define APECS_MEM_B3BAR  		(IDENT_ADDR + 0x180000860UL)

#define APECS_MEM_B4BAR  		(IDENT_ADDR + 0x180000880UL)

#define APECS_MEM_B5BAR  		(IDENT_ADDR + 0x1800008A0UL)

#define APECS_MEM_B6BAR  		(IDENT_ADDR + 0x1800008C0UL)

#define APECS_MEM_B7BAR  		(IDENT_ADDR + 0x1800008E0UL)

#define APECS_MEM_B8BAR  		(IDENT_ADDR + 0x180000900UL)



/* Bank x Configuration Register */

#define APECS_MEM_B0BCR  		(IDENT_ADDR + 0x180000A00UL)

#define APECS_MEM_B1BCR  		(IDENT_ADDR + 0x180000A20UL)

#define APECS_MEM_B2BCR  		(IDENT_ADDR + 0x180000A40UL)

#define APECS_MEM_B3BCR  		(IDENT_ADDR + 0x180000A60UL)

#define APECS_MEM_B4BCR  		(IDENT_ADDR + 0x180000A80UL)

#define APECS_MEM_B5BCR  		(IDENT_ADDR + 0x180000AA0UL)

#define APECS_MEM_B6BCR  		(IDENT_ADDR + 0x180000AC0UL)

#define APECS_MEM_B7BCR  		(IDENT_ADDR + 0x180000AE0UL)

#define APECS_MEM_B8BCR  		(IDENT_ADDR + 0x180000B00UL)



/* Bank x Timing Register A */

#define APECS_MEM_B0TRA  		(IDENT_ADDR + 0x180000C00UL)

#define APECS_MEM_B1TRA  		(IDENT_ADDR + 0x180000C20UL)

#define APECS_MEM_B2TRA  		(IDENT_ADDR + 0x180000C40UL)

#define APECS_MEM_B3TRA  		(IDENT_ADDR + 0x180000C60UL)

#define APECS_MEM_B4TRA  		(IDENT_ADDR + 0x180000C80UL)

#define APECS_MEM_B5TRA  		(IDENT_ADDR + 0x180000CA0UL)

#define APECS_MEM_B6TRA  		(IDENT_ADDR + 0x180000CC0UL)

#define APECS_MEM_B7TRA  		(IDENT_ADDR + 0x180000CE0UL)

#define APECS_MEM_B8TRA  		(IDENT_ADDR + 0x180000D00UL)



/* Bank x Timing Register B */

#define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)

#define APECS_MEM_B1TRB  		(IDENT_ADDR + 0x180000E20UL)

#define APECS_MEM_B2TRB  		(IDENT_ADDR + 0x180000E40UL)

#define APECS_MEM_B3TRB  		(IDENT_ADDR + 0x180000E60UL)

#define APECS_MEM_B4TRB  		(IDENT_ADDR + 0x180000E80UL)

#define APECS_MEM_B5TRB  		(IDENT_ADDR + 0x180000EA0UL)

#define APECS_MEM_B6TRB  		(IDENT_ADDR + 0x180000EC0UL)

#define APECS_MEM_B7TRB  		(IDENT_ADDR + 0x180000EE0UL)

#define APECS_MEM_B8TRB  		(IDENT_ADDR + 0x180000F00UL)





/*

 * Memory spaces:

 */

#define APECS_IACK_SC		        (IDENT_ADDR + 0x1b0000000UL)

#define APECS_CONF		        (IDENT_ADDR + 0x1e0000000UL)

#define APECS_IO			(IDENT_ADDR + 0x1c0000000UL)

#define APECS_SPARSE_MEM		(IDENT_ADDR + 0x200000000UL)

#define APECS_DENSE_MEM		        (IDENT_ADDR + 0x300000000UL)





/*

 * Bit definitions for I/O Controller status register 0:

 */

#define APECS_IOC_STAT0_CMD		0xf

#define APECS_IOC_STAT0_ERR		(1<<4)

#define APECS_IOC_STAT0_LOST		(1<<5)

#define APECS_IOC_STAT0_THIT		(1<<6)

#define APECS_IOC_STAT0_TREF		(1<<7)

#define APECS_IOC_STAT0_CODE_SHIFT	8

#define APECS_IOC_STAT0_CODE_MASK	0x7

#define APECS_IOC_STAT0_P_NBR_SHIFT	13

#define APECS_IOC_STAT0_P_NBR_MASK	0x7ffff



#define APECS_HAE_ADDRESS		APECS_IOC_HAXR1





/*

 * Data structure for handling APECS machine checks:

 */



struct el_apecs_mikasa_sysdata_mcheck

{

	unsigned long coma_gcr;

	unsigned long coma_edsr;

	unsigned long coma_ter;

	unsigned long coma_elar;

	unsigned long coma_ehar;

	unsigned long coma_ldlr;

	unsigned long coma_ldhr;

	unsigned long coma_base0;

	unsigned long coma_base1;

	unsigned long coma_base2;

	unsigned long coma_base3;

	unsigned long coma_cnfg0;

	unsigned long coma_cnfg1;

	unsigned long coma_cnfg2;

	unsigned long coma_cnfg3;

	unsigned long epic_dcsr;

	unsigned long epic_pear;

	unsigned long epic_sear;

	unsigned long epic_tbr1;

	unsigned long epic_tbr2;

	unsigned long epic_pbr1;

	unsigned long epic_pbr2;

	unsigned long epic_pmr1;

	unsigned long epic_pmr2;

	unsigned long epic_harx1;

	unsigned long epic_harx2;

	unsigned long epic_pmlt;

	unsigned long epic_tag0;

	unsigned long epic_tag1;

	unsigned long epic_tag2;

	unsigned long epic_tag3;

	unsigned long epic_tag4;

	unsigned long epic_tag5;

	unsigned long epic_tag6;

	unsigned long epic_tag7;

	unsigned long epic_data0;

	unsigned long epic_data1;

	unsigned long epic_data2;

	unsigned long epic_data3;

	unsigned long epic_data4;

	unsigned long epic_data5;

	unsigned long epic_data6;

	unsigned long epic_data7;



	unsigned long pceb_vid;

	unsigned long pceb_did;

	unsigned long pceb_revision;

	unsigned long pceb_command;

	unsigned long pceb_status;

	unsigned long pceb_latency;

	unsigned long pceb_control;

	unsigned long pceb_arbcon;

	unsigned long pceb_arbpri;



	unsigned long esc_id;

	unsigned long esc_revision;

	unsigned long esc_int0;

	unsigned long esc_int1;

	unsigned long esc_elcr0;

	unsigned long esc_elcr1;

	unsigned long esc_last_eisa;

	unsigned long esc_nmi_stat;



	unsigned long pci_ir;

	unsigned long pci_imr;

	unsigned long svr_mgr;

};



/* This for the normal APECS machines.  */

struct el_apecs_sysdata_mcheck

{

	unsigned long coma_gcr;

	unsigned long coma_edsr;

	unsigned long coma_ter;

	unsigned long coma_elar;

	unsigned long coma_ehar;

	unsigned long coma_ldlr;

	unsigned long coma_ldhr;

	unsigned long coma_base0;

	unsigned long coma_base1;

	unsigned long coma_base2;

	unsigned long coma_cnfg0;

	unsigned long coma_cnfg1;

	unsigned long coma_cnfg2;

	unsigned long epic_dcsr;

	unsigned long epic_pear;

	unsigned long epic_sear;

	unsigned long epic_tbr1;

	unsigned long epic_tbr2;

	unsigned long epic_pbr1;

	unsigned long epic_pbr2;

	unsigned long epic_pmr1;

	unsigned long epic_pmr2;

	unsigned long epic_harx1;

	unsigned long epic_harx2;

	unsigned long epic_pmlt;

	unsigned long epic_tag0;

	unsigned long epic_tag1;

	unsigned long epic_tag2;

	unsigned long epic_tag3;

	unsigned long epic_tag4;

	unsigned long epic_tag5;

	unsigned long epic_tag6;

	unsigned long epic_tag7;

	unsigned long epic_data0;

	unsigned long epic_data1;

	unsigned long epic_data2;

	unsigned long epic_data3;

	unsigned long epic_data4;

	unsigned long epic_data5;

	unsigned long epic_data6;

	unsigned long epic_data7;

};



struct el_apecs_procdata

{

	unsigned long paltemp[32];  /* PAL TEMP REGS. */

	/* EV4-specific fields */

	unsigned long exc_addr;     /* Address of excepting instruction. */

	unsigned long exc_sum;      /* Summary of arithmetic traps. */

	unsigned long exc_mask;     /* Exception mask (from exc_sum). */

	unsigned long iccsr;        /* IBox hardware enables. */

	unsigned long pal_base;     /* Base address for PALcode. */

	unsigned long hier;         /* Hardware Interrupt Enable. */

	unsigned long hirr;         /* Hardware Interrupt Request. */

	unsigned long csr;          /* D-stream fault info. */

	unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */

	unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */

	unsigned long abox_ctl;     /* ABox Control Register. */

	unsigned long biu_stat;     /* BIU Status. */

	unsigned long biu_addr;     /* BUI Address. */

	unsigned long biu_ctl;      /* BIU Control. */

	unsigned long fill_syndrome;/* For correcting ECC errors. */

	unsigned long fill_addr;    /* Cache block which was being read */

	unsigned long va;           /* Effective VA of fault or miss. */

	unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/

};





#ifdef __KERNEL__



#ifndef __EXTERN_INLINE

#define __EXTERN_INLINE extern inline

#define __IO_EXTERN_INLINE

#endif



/*

 * I/O functions:

 *

 * Unlike Jensen, the APECS machines have no concept of local

 * I/O---everything goes over the PCI bus.

 *

 * There is plenty room for optimization here.  In particular,

 * the Alpha's insb/insw/extb/extw should be useful in moving

 * data to/from the right byte-lanes.

 */



#define vip	volatile int __force *

#define vuip	volatile unsigned int __force *

#define vulp	volatile unsigned long __force *



#define APECS_SET_HAE						\

	do {							\

		if (addr >= (1UL << 24)) {			\

			unsigned long msb = addr & 0xf8000000;	\

			addr -= msb;				\

			set_hae(msb);				\

		}						\

	} while (0)



__EXTERN_INLINE u8 apecs_ioread8(const void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	unsigned long result, base_and_type;



	if (addr >= APECS_DENSE_MEM) {

		addr -= APECS_DENSE_MEM;

		APECS_SET_HAE;

		base_and_type = APECS_SPARSE_MEM + 0x00;

	} else {

		addr -= APECS_IO;

		base_and_type = APECS_IO + 0x00;

	}



	result = *(vip) ((addr << 5) + base_and_type);

	return __kernel_extbl(result, addr & 3);

}



__EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	unsigned long w, base_and_type;



	if (addr >= APECS_DENSE_MEM) {

		addr -= APECS_DENSE_MEM;

		APECS_SET_HAE;

		base_and_type = APECS_SPARSE_MEM + 0x00;

	} else {

		addr -= APECS_IO;

		base_and_type = APECS_IO + 0x00;

	}



	w = __kernel_insbl(b, addr & 3);

	*(vuip) ((addr << 5) + base_and_type) = w;

}



__EXTERN_INLINE u16 apecs_ioread16(const void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	unsigned long result, base_and_type;



	if (addr >= APECS_DENSE_MEM) {

		addr -= APECS_DENSE_MEM;

		APECS_SET_HAE;

		base_and_type = APECS_SPARSE_MEM + 0x08;

	} else {

		addr -= APECS_IO;

		base_and_type = APECS_IO + 0x08;

	}



	result = *(vip) ((addr << 5) + base_and_type);

	return __kernel_extwl(result, addr & 3);

}



__EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	unsigned long w, base_and_type;



	if (addr >= APECS_DENSE_MEM) {

		addr -= APECS_DENSE_MEM;

		APECS_SET_HAE;

		base_and_type = APECS_SPARSE_MEM + 0x08;

	} else {

		addr -= APECS_IO;

		base_and_type = APECS_IO + 0x08;

	}



	w = __kernel_inswl(b, addr & 3);

	*(vuip) ((addr << 5) + base_and_type) = w;

}



__EXTERN_INLINE u32 apecs_ioread32(const void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	if (addr < APECS_DENSE_MEM)

		addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;

	return *(vuip)addr;

}



__EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	if (addr < APECS_DENSE_MEM)

		addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;

	*(vuip)addr = b;

}



__EXTERN_INLINE u64 apecs_ioread64(const void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	if (addr < APECS_DENSE_MEM)

		addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;

	return *(vulp)addr;

}



__EXTERN_INLINE void apecs_iowrite64(u64 b, void __iomem *xaddr)

{

	unsigned long addr = (unsigned long) xaddr;

	if (addr < APECS_DENSE_MEM)

		addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;

	*(vulp)addr = b;

}



__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)

{

	return (void __iomem *)(addr + APECS_IO);

}



__EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,

					    unsigned long size)

{

	return (void __iomem *)(addr + APECS_DENSE_MEM);

}



__EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)

{

	return addr >= IDENT_ADDR + 0x180000000UL;

}



__EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)

{

	return (unsigned long)addr >= APECS_DENSE_MEM;

}



#undef APECS_SET_HAE



#undef vip

#undef vuip

#undef vulp



#undef __IO_PREFIX

#define __IO_PREFIX		apecs

#define apecs_trivial_io_bw	0

#define apecs_trivial_io_lq	0

#define apecs_trivial_rw_bw	2

#define apecs_trivial_rw_lq	1

#define apecs_trivial_iounmap	1

#include <asm/io_trivial.h>



#ifdef __IO_EXTERN_INLINE

#undef __EXTERN_INLINE

#undef __IO_EXTERN_INLINE

#endif



#endif /* __KERNEL__ */



#endif /* __ALPHA_APECS__H__ */

arch/alpha/include/asm/core_lca.h

deleted100644 → 0
+0 −378

File deleted.

Preview size limit exceeded, changes collapsed.

arch/alpha/include/asm/dma.h

+1 −8

File changed.

Preview size limit exceeded, changes collapsed.

arch/alpha/include/asm/io.h

+1 −5
Original line number Diff line number Diff line
@@ -203,14 +203,10 @@ static inline int generic_is_mmio(const volatile void __iomem *a) 


#else



#if defined(CONFIG_ALPHA_APECS)

# include <asm/core_apecs.h>

#elif defined(CONFIG_ALPHA_CIA)

#if defined(CONFIG_ALPHA_CIA)

# include <asm/core_cia.h>

#elif defined(CONFIG_ALPHA_IRONGATE)

# include <asm/core_irongate.h>

#elif defined(CONFIG_ALPHA_LCA)

# include <asm/core_lca.h>

#elif defined(CONFIG_ALPHA_MARVEL)

# include <asm/core_marvel.h>

#elif defined(CONFIG_ALPHA_MCPCIA)