Commit 4310acd4 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add ring flag for no user submissions 



This would be set by IPs which only accept submissions
from the kernel, not userspace, such as when kernel
queues are disabled. Don't expose the rings to userspace
and reject any submissions in the CS IOCTL.

v2: fix error code (Alex)

Reviewed-by: default avatarSunil <Khatri&lt;sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a96a787d

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+4 −0
Original line number Diff line number Diff line
@@ -349,6 +349,10 @@ static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p, 
	ring = amdgpu_job_ring(job);

	ib = &job->ibs[job->num_ibs++];



	/* submissions to kernel queues are disabled */

	if (ring->no_user_submission)

		return -EINVAL;



	/* MM engine doesn't support user fences */

	if (p->uf_bo && ring->funcs->no_user_fence)

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+20 −10
Original line number Diff line number Diff line
@@ -408,7 +408,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
	case AMDGPU_HW_IP_GFX:

		type = AMD_IP_BLOCK_TYPE_GFX;

		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			if (adev->gfx.gfx_ring[i].sched.ready)

			if (adev->gfx.gfx_ring[i].sched.ready &&

			    !adev->gfx.gfx_ring[i].no_user_submission)

				++num_rings;

		ib_start_alignment = 32;

		ib_size_alignment = 32;
@@ -416,7 +417,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
	case AMDGPU_HW_IP_COMPUTE:

		type = AMD_IP_BLOCK_TYPE_GFX;

		for (i = 0; i < adev->gfx.num_compute_rings; i++)

			if (adev->gfx.compute_ring[i].sched.ready)

			if (adev->gfx.compute_ring[i].sched.ready &&

			    !adev->gfx.compute_ring[i].no_user_submission)

				++num_rings;

		ib_start_alignment = 32;

		ib_size_alignment = 32;
@@ -424,7 +426,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
	case AMDGPU_HW_IP_DMA:

		type = AMD_IP_BLOCK_TYPE_SDMA;

		for (i = 0; i < adev->sdma.num_instances; i++)

			if (adev->sdma.instance[i].ring.sched.ready)

			if (adev->sdma.instance[i].ring.sched.ready &&

			    !adev->gfx.gfx_ring[i].no_user_submission)

				++num_rings;

		ib_start_alignment = 256;

		ib_size_alignment = 4;
@@ -435,7 +438,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
			if (adev->uvd.harvest_config & (1 << i))

				continue;



			if (adev->uvd.inst[i].ring.sched.ready)

			if (adev->uvd.inst[i].ring.sched.ready &&

			    !adev->uvd.inst[i].ring.no_user_submission)

				++num_rings;

		}

		ib_start_alignment = 256;
@@ -444,7 +448,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
	case AMDGPU_HW_IP_VCE:

		type = AMD_IP_BLOCK_TYPE_VCE;

		for (i = 0; i < adev->vce.num_rings; i++)

			if (adev->vce.ring[i].sched.ready)

			if (adev->vce.ring[i].sched.ready &&

			    !adev->vce.ring[i].no_user_submission)

				++num_rings;

		ib_start_alignment = 256;

		ib_size_alignment = 4;
@@ -456,7 +461,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
				continue;



			for (j = 0; j < adev->uvd.num_enc_rings; j++)

				if (adev->uvd.inst[i].ring_enc[j].sched.ready)

				if (adev->uvd.inst[i].ring_enc[j].sched.ready &&

				    !adev->uvd.inst[i].ring_enc[j].no_user_submission)

					++num_rings;

		}

		ib_start_alignment = 256;
@@ -468,7 +474,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
			if (adev->vcn.harvest_config & (1 << i))

				continue;



			if (adev->vcn.inst[i].ring_dec.sched.ready)

			if (adev->vcn.inst[i].ring_dec.sched.ready &&

			    !adev->vcn.inst[i].ring_dec.no_user_submission)

				++num_rings;

		}

		ib_start_alignment = 256;
@@ -481,7 +488,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
				continue;



			for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++)

				if (adev->vcn.inst[i].ring_enc[j].sched.ready)

				if (adev->vcn.inst[i].ring_enc[j].sched.ready &&

				    !adev->vcn.inst[i].ring_enc[j].no_user_submission)

					++num_rings;

		}

		ib_start_alignment = 256;
@@ -496,7 +504,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
				continue;



			for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)

				if (adev->jpeg.inst[i].ring_dec[j].sched.ready)

				if (adev->jpeg.inst[i].ring_dec[j].sched.ready &&

				    !adev->jpeg.inst[i].ring_dec[j].no_user_submission)

					++num_rings;

		}

		ib_start_alignment = 256;
@@ -504,7 +513,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 
		break;

	case AMDGPU_HW_IP_VPE:

		type = AMD_IP_BLOCK_TYPE_VPE;

		if (adev->vpe.ring.sched.ready)

		if (adev->vpe.ring.sched.ready &&

		    !adev->vpe.ring.no_user_submission)

			++num_rings;

		ib_start_alignment = 256;

		ib_size_alignment = 4;

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+1 −1
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ struct amdgpu_ring { 
	struct dma_fence	*vmid_wait;

	bool			has_compute_vm_bug;

	bool			no_scheduler;

	bool			no_user_submission;

	int			hw_prio;

	unsigned 		num_hw_submission;

	atomic_t		*sched_score;
@@ -305,7 +306,6 @@ struct amdgpu_ring { 
	unsigned int    entry_index;

	/* store the cached rptr to restore after reset */

	uint64_t cached_rptr;



};



#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))