Commit 43193c79 authored by AMD\ktsao's avatar AMD\ktsao Committed by Alex Deucher
Browse files

drm/amd/display: remove DCN1 guard as DCN1 is already open sourced. 



Signed-off-by: default avatarKenny Tsao <kenny.tsao@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7a09f5be

drivers/gpu/drm/amd/display/dc/dc.h

+0 −6
Original line number Diff line number Diff line
@@ -96,13 +96,9 @@ struct dc_surface; 
struct validate_context;



struct dc_cap_funcs {

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	bool (*get_dcc_compression_cap)(const struct dc *dc,

			const struct dc_dcc_surface_param *input,

			struct dc_surface_dcc_cap *output);

#else

	int i;

#endif

};



struct dc_stream_funcs {
@@ -171,7 +167,6 @@ struct dc_debug { 
	bool disable_stutter;

	bool disable_dcc;

	bool disable_dfs_bypass;

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	bool disable_dpp_power_gate;

	bool disable_hubp_power_gate;

	bool disable_pplib_wm_range;
@@ -185,7 +180,6 @@ struct dc_debug { 
	int percent_of_ideal_drambw;

	int dram_clock_change_latency_ns;

	int always_scale;

#endif

	bool disable_pplib_clock_request;

	bool disable_clock_gate;

	bool disable_dmcu;

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

+43 −48
Original line number Diff line number Diff line
@@ -54,7 +54,6 @@ 
	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \

	SR(BIOS_SCRATCH_2)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define ABM_DCN10_REG_LIST(id)\

	ABM_COMMON_REG_LIST_DCE_BASE(), \

	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
@@ -68,7 +67,6 @@ 
	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \

	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \

	NBIO_SR(BIOS_SCRATCH_2)

#endif



#define ABM_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -120,8 +118,6 @@ 
	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \

			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)





#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define ABM_MASK_SH_LIST_DCN10(mask_sh) \

	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \

	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -152,7 +148,6 @@ 
			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \

	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \

			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)

#endif



#define ABM_REG_FIELD_LIST(type) \

	type ABM1_HG_NUM_OF_BINS_SEL; \

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

+0 −2
Original line number Diff line number Diff line
@@ -55,7 +55,6 @@ 
	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \

		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

		SRII(PHASE, DP_DTO, 0),\
@@ -74,7 +73,6 @@ 
#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\

	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)

#endif



#define CS_REG_FIELD_LIST(type) \

	type PLL_REF_DIV_SRC; \

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

+7 −13
Original line number Diff line number Diff line
@@ -48,11 +48,9 @@ 
	DMCU_COMMON_REG_LIST_DCE_BASE(), \

	SR(DCI_MEM_PWR_STATUS)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define DMCU_DCN10_REG_LIST()\

	DMCU_COMMON_REG_LIST_DCE_BASE(), \

	SR(DMU_MEM_PWR_CNTL)

#endif



#define DMCU_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -82,12 +80,10 @@ 
	DMCU_SF(DCI_MEM_PWR_STATUS, \

		DMCU_IRAM_MEM_PWR_STATE, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define DMCU_MASK_SH_LIST_DCN10(mask_sh) \

	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \

	DMCU_SF(DMU_MEM_PWR_CNTL, \

			DMCU_IRAM_MEM_PWR_STATE, mask_sh)

#endif



#define DMCU_REG_FIELD_LIST(type) \

	type DMCU_IRAM_MEM_PWR_STATE; \
@@ -211,13 +207,11 @@ struct dmcu *dce_dmcu_create( 
	const struct dce_dmcu_shift *dmcu_shift,

	const struct dce_dmcu_mask *dmcu_mask);



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

struct dmcu *dcn10_dmcu_create(

	struct dc_context *ctx,

	const struct dce_dmcu_registers *regs,

	const struct dce_dmcu_shift *dmcu_shift,

	const struct dce_dmcu_mask *dmcu_mask);

#endif



void dce_dmcu_destroy(struct dmcu **dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

+6 −9
Original line number Diff line number Diff line
@@ -100,15 +100,12 @@ 
	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

	SR(DCI_MEM_PWR_STATUS)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#define LE_DCN10_REG_LIST(id)\

	LE_COMMON_REG_LIST_BASE(id), \

	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

	SR(DMU_MEM_PWR_CNTL)

#endif





struct dce110_link_enc_aux_registers {

	uint32_t AUX_CONTROL;