Commit 43319897 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v6.18-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC fix from Ulf Hansson:

 - sdhci-of-dwcmshc: Fix reset handling for some variants

* tag 'mmc-v6.18-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-of-dwcmshc: Promote the th1520 reset handling to ip level
parents f849f26f 74752872

drivers/mmc/host/sdhci-of-dwcmshc.c

+17 −12
Original line number Diff line number Diff line
@@ -289,6 +289,19 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 
	sdhci_adma_write_desc(host, desc, addr, len, cmd);

}



static void dwcmshc_reset(struct sdhci_host *host, u8 mask)

{

	sdhci_reset(host, mask);



	/* The dwcmshc does not comply with the SDHCI specification

	 * regarding the "Software Reset for CMD line should clear 'Command

	 * Complete' in the Normal Interrupt Status Register." Clear the bit

	 * here to compensate for this quirk.

	 */

	if (mask & SDHCI_RESET_CMD)

		sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);

}



static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)

{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -832,15 +845,7 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) 
	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);

	u16 ctrl_2;



	sdhci_reset(host, mask);



	/* The T-Head 1520 SoC does not comply with the SDHCI specification

	 * regarding the "Software Reset for CMD line should clear 'Command

	 * Complete' in the Normal Interrupt Status Register." Clear the bit

	 * here to compensate for this quirk.

	 */

	if (mask & SDHCI_RESET_CMD)

		sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);

	dwcmshc_reset(host, mask);



	if (priv->flags & FLAG_IO_FIXED_1V8) {

		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
@@ -886,7 +891,7 @@ static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) 
	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);

	u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;



	sdhci_reset(host, mask);

	dwcmshc_reset(host, mask);



	if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {

		val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
@@ -958,7 +963,7 @@ static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 
	val |= SDHCI_INT_DATA_AVAIL;

	sdhci_writel(host, val, SDHCI_INT_STATUS);



	sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);

	dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);

}



static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
@@ -1100,7 +1105,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { 
	.set_bus_width		= sdhci_set_bus_width,

	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,

	.get_max_clock		= dwcmshc_get_max_clock,

	.reset			= sdhci_reset,

	.reset			= dwcmshc_reset,

	.adma_write_desc	= dwcmshc_adma_write_desc,

	.irq			= dwcmshc_cqe_irq_handler,

};