Commit 437330d9 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/mops' into for-next/core 

* for-next/mops:
  : More FEAT_MOPS (memcpy instructions) uses - in-kernel routines
  arm64: mops: Document requirements for hypervisors
  arm64: lib: Use MOPS for copy_page() and clear_page()
  arm64: lib: Use MOPS for memcpy() routines
  arm64: mops: Document booting requirement for HCR_EL2.MCE2
  arm64: mops: Handle MOPS exceptions from EL1
  arm64: probes: Disable kprobes/uprobes on MOPS instructions

# Conflicts:
#	arch/arm64/kernel/entry-common.c
parents 5a433206 2cfdb799

Documentation/arch/arm64/booting.rst

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@@ -388,6 +388,9 @@ Before jumping into the kernel, the following conditions must be met: 


    - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.



    - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor

      must handle MOPS exceptions as described in :ref:`arm64_mops_hyp`.



  For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):



  - If EL3 is present:

Documentation/arch/arm64/index.rst

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@@ -22,6 +22,7 @@ ARM64 Architecture 
    legacy_instructions

    memory

    memory-tagging-extension

    mops

    perf

    pointer-authentication

    ptdump

Documentation/arch/arm64/mops.rst

0 → 100644
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.. SPDX-License-Identifier: GPL-2.0



===================================

Memory copy/set instructions (MOPS)

===================================



A MOPS memory copy/set operation consists of three consecutive CPY* or SET*

instructions: a prologue, main and epilogue (for example: CPYP, CPYM, CPYE).



A main or epilogue instruction can take a MOPS exception for various reasons,

for example when a task is migrated to a CPU with a different MOPS

implementation, or when the instruction's alignment and size requirements are

not met. The software exception handler is then expected to reset the registers

and restart execution from the prologue instruction. Normally this is handled

by the kernel.



For more details refer to "D1.3.5.7 Memory Copy and Memory Set exceptions" in

the Arm Architecture Reference Manual DDI 0487K.a (Arm ARM).



.. _arm64_mops_hyp:



Hypervisor requirements

-----------------------



A hypervisor running a Linux guest must handle all MOPS exceptions from the

guest kernel, as Linux may not be able to handle the exception at all times.

For example, a MOPS exception can be taken when the hypervisor migrates a vCPU

to another physical CPU with a different MOPS implementation.



To do this, the hypervisor must:



  - Set HCRX_EL2.MCE2 to 1 so that the exception is taken to the hypervisor.



  - Have an exception handler that implements the algorithm from the Arm ARM

    rules CNTMJ and MWFQH.



  - Set the guest's PSTATE.SS to 0 in the exception handler, to handle a

    potential step of the current instruction.



    Note: Clearing PSTATE.SS is needed so that a single step exception is taken

    on the next instruction (the prologue instruction). Otherwise prologue

    would get silently stepped over and the single step exception taken on the

    main instruction. Note that if the guest instruction is not being stepped

    then clearing PSTATE.SS has no effect.

arch/arm64/Kconfig

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@@ -2160,6 +2160,9 @@ config ARM64_EPAN 
	  if the cpu does not implement the feature.

endmenu # "ARMv8.7 architectural features"



config AS_HAS_MOPS

	def_bool $(as-instr,.arch_extension mops)



menu "ARMv8.9 architectural features"



config ARM64_POE

arch/arm64/include/asm/debug-monitors.h

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@@ -105,6 +105,7 @@ void kernel_enable_single_step(struct pt_regs *regs); 
void kernel_disable_single_step(void);

int kernel_active_single_step(void);

void kernel_rewind_single_step(struct pt_regs *regs);

void kernel_fastforward_single_step(struct pt_regs *regs);



#ifdef CONFIG_HAVE_HW_BREAKPOINT

int reinstall_suspended_bps(struct pt_regs *regs);