Commit 438d3fc4 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Rob Herring
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dt-bindings: clock: keystone: remove unstable remark 



Keystone clock controller bindings were marked as work-in-progress /
unstable in 2013 in commit b9e0d40c ("clk: keystone: add Keystone
PLL clock driver") and commit 7affe568 ("clk: keystone: Add gate
control clock driver") Almost eleven years is enough, so drop the
"unstable" remark and expect usual ABI rules.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240224091236.10146-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent a1aa5390

Documentation/devicetree/bindings/clock/keystone-gate.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for Keystone gate control driver which uses PSC controller IP.



This binding uses the common clock binding[1].

Documentation/devicetree/bindings/clock/keystone-pll.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for keystone PLLs. The main PLL IP typically has a multiplier,

a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL

and PAPLL are controlled by the memory mapped register where as the Main