Commit 43eb9a8a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/mdss: define bitfields for the UBWC_STATIC register 



Rather than hand-coding UBWC_STATIC value calculation, define
corresponding bitfields and use them to setup the register value.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/626372/
Link: https://lore.kernel.org/r/20241127-msm-mdss-ubwc-v3-1-9782a7c2b023@linaro.org
parent 1a40bb31

drivers/gpu/drm/msm/msm_mdss.c

+22 −16
Original line number Diff line number Diff line
@@ -173,15 +173,17 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 
static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)

{

	const struct msm_mdss_data *data = msm_mdss->mdss_data;

	u32 value = (data->ubwc_swizzle & 0x1) |

		    (data->highest_bank_bit & 0x3) << 4 |

		    (data->macrotile_mode & 0x1) << 12;

	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |

		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);



	if (data->macrotile_mode)

		value |= MDSS_UBWC_STATIC_MACROTILE_MODE;



	if (data->ubwc_enc_version == UBWC_3_0)

		value |= BIT(10);

		value |= MDSS_UBWC_STATIC_UBWC_AMSBC;



	if (data->ubwc_enc_version == UBWC_1_0)

		value |= BIT(8);

		value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1);



	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

}
@@ -189,10 +191,14 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 
static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)

{

	const struct msm_mdss_data *data = msm_mdss->mdss_data;

	u32 value = (data->ubwc_swizzle & 0x7) |

		    (data->ubwc_static & 0x1) << 3 |

		    (data->highest_bank_bit & 0x7) << 4 |

		    (data->macrotile_mode & 0x1) << 12;

	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |

		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);



	if (data->ubwc_bank_spread)

		value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;



	if (data->macrotile_mode)

		value |= MDSS_UBWC_STATIC_MACROTILE_MODE;



	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
@@ -572,7 +578,7 @@ static const struct msm_mdss_data sa8775p_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_0,

	.ubwc_swizzle = 4,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	.highest_bank_bit = 0,

	.macrotile_mode = 1,

	.reg_bus_bw = 74000,
@@ -590,7 +596,7 @@ static const struct msm_mdss_data sc7280_data = { 
	.ubwc_enc_version = UBWC_3_0,

	.ubwc_dec_version = UBWC_4_0,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	.highest_bank_bit = 1,

	.macrotile_mode = 1,

	.reg_bus_bw = 74000,
@@ -608,7 +614,7 @@ static const struct msm_mdss_data sc8280xp_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_0,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	.highest_bank_bit = 3,

	.macrotile_mode = 1,

	.reg_bus_bw = 76800,
@@ -671,7 +677,7 @@ static const struct msm_mdss_data sm8250_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_0,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	/* TODO: highest_bank_bit = 2 for LP_DDR4 */

	.highest_bank_bit = 3,

	.macrotile_mode = 1,
@@ -682,7 +688,7 @@ static const struct msm_mdss_data sm8350_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_0,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	/* TODO: highest_bank_bit = 2 for LP_DDR4 */

	.highest_bank_bit = 3,

	.macrotile_mode = 1,
@@ -693,7 +699,7 @@ static const struct msm_mdss_data sm8550_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_3,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	/* TODO: highest_bank_bit = 2 for LP_DDR4 */

	.highest_bank_bit = 3,

	.macrotile_mode = 1,
@@ -704,7 +710,7 @@ static const struct msm_mdss_data x1e80100_data = { 
	.ubwc_enc_version = UBWC_4_0,

	.ubwc_dec_version = UBWC_4_3,

	.ubwc_swizzle = 6,

	.ubwc_static = 1,

	.ubwc_bank_spread = true,

	/* TODO: highest_bank_bit = 2 for LP_DDR4 */

	.highest_bank_bit = 3,

	.macrotile_mode = 1,

drivers/gpu/drm/msm/msm_mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ struct msm_mdss_data { 
	u32 ubwc_swizzle;

	u32 ubwc_static;

	u32 highest_bank_bit;

	bool ubwc_bank_spread;

	u32 macrotile_mode;

	u32 reg_bus_bw;

};

drivers/gpu/drm/msm/registers/display/mdss.xml

+10 −1
Original line number Diff line number Diff line
@@ -21,7 +21,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 


	<reg32 offset="0x00058" name="UBWC_DEC_HW_VERSION"/>



	<reg32 offset="0x00144" name="UBWC_STATIC"/>

	<reg32 offset="0x00144" name="UBWC_STATIC">

		<bitfield name="UBWC_SWIZZLE" low="0" high="2"/>

		<bitfield name="UBWC_BANK_SPREAD" pos="3"/>

		<!-- high=5 for UBWC < 4.0 -->

		<bitfield name="HIGHEST_BANK_BIT" low="4" high="6"/>

		<bitfield name="UBWC_MIN_ACC_LEN" low="8" high="9"/>

		<bitfield name="UBWC_AMSBC" pos="10"/>

		<bitfield name="MACROTILE_MODE" pos="12"/>

	</reg32>



	<reg32 offset="0x00150" name="UBWC_CTRL_2"/>

	<reg32 offset="0x00154" name="UBWC_PREDICTION_MODE"/>

</domain>