Commit 43ef6c22 authored by Gayatri Kammela's avatar Gayatri Kammela Committed by Hans de Goede
Browse files

platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake 



Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information
and supports a few additional registers. Hence add the LTR registers
specific to Tiger Lake to the cnp_ltr_show_map[].

Also adjust the number of LTR IPs for Tiger Lake to the correct amount.

Signed-off-by: default avatarGayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarRajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20210417031252.3020837-9-david.e.box@linux.intel.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 8074a79f

drivers/platform/x86/intel_pmc_core.c

+2 −0
Original line number Diff line number Diff line
@@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { 
	 * a list of core SoCs using this.

	 */

	{"WIGIG",		ICL_PMC_LTR_WIGIG},

	{"THC0",                TGL_PMC_LTR_THC0},

	{"THC1",                TGL_PMC_LTR_THC1},

	/* Below two cannot be used for LTR_IGNORE */

	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},

	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},

drivers/platform/x86/intel_pmc_core.h

+3 −1
Original line number Diff line number Diff line
@@ -191,8 +191,10 @@ enum ppfear_regs { 
#define GET_X2_COUNTER(v)			((v) >> 1)

#define LPM_STS_LATCH_MODE			BIT(31)



#define TGL_NUM_IP_IGN_ALLOWED			22

#define TGL_PMC_SLP_S0_RES_COUNTER_STEP		0x7A

#define TGL_PMC_LTR_THC0			0x1C04

#define TGL_PMC_LTR_THC1			0x1C08

#define TGL_NUM_IP_IGN_ALLOWED			23

#define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */



/*