Commit 444b46a1 authored by Xin Li (Intel)'s avatar Xin Li (Intel) Committed by Ingo Molnar
Browse files

x86/msr: Replace wrmsr(msr, low, 0) with wrmsrq(msr, low) 



The third argument in wrmsr(msr, low, 0) is unnecessary.  Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.

Signed-off-by: default avatarXin Li (Intel) <xin@zytor.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Uros Bizjak <ubizjak@gmail.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Link: https://lore.kernel.org/r/20250427092027.1598740-15-xin@zytor.com
parent 0c2678ef

arch/x86/hyperv/hv_apic.c

+3 −3
Original line number Diff line number Diff line
@@ -76,10 +76,10 @@ static void hv_apic_write(u32 reg, u32 val) 
{

	switch (reg) {

	case APIC_EOI:

		wrmsr(HV_X64_MSR_EOI, val, 0);

		wrmsrq(HV_X64_MSR_EOI, val);

		break;

	case APIC_TASKPRI:

		wrmsr(HV_X64_MSR_TPR, val, 0);

		wrmsrq(HV_X64_MSR_TPR, val);

		break;

	default:

		native_apic_mem_write(reg, val);
@@ -93,7 +93,7 @@ static void hv_apic_eoi_write(void) 
	if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))

		return;



	wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0);

	wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK);

}



static bool cpu_is_self(int cpu)

arch/x86/include/asm/apic.h

+1 −1
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static inline void native_apic_msr_write(u32 reg, u32 v) 
	    reg == APIC_LVR)

		return;



	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);

	wrmsrq(APIC_BASE_MSR + (reg >> 4), v);

}



static inline void native_apic_msr_eoi(void)

arch/x86/include/asm/switch_to.h

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ static inline void refresh_sysenter_cs(struct thread_struct *thread) 
		return;



	this_cpu_write(cpu_tss_rw.x86_tss.ss1, thread->sysenter_cs);

	wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);

	wrmsrq(MSR_IA32_SYSENTER_CS, thread->sysenter_cs);

}

#endif

arch/x86/kernel/cpu/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -1207,7 +1207,7 @@ void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 
	if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)

		return;



	wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);

	wrmsrq(amd_msr_dr_addr_masks[dr], mask);

	per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;

}

arch/x86/kernel/cpu/common.c

+4 −4
Original line number Diff line number Diff line
@@ -1982,9 +1982,9 @@ void enable_sep_cpu(void) 
	 */



	tss->x86_tss.ss1 = __KERNEL_CS;

	wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);

	wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);

	wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);

	wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1);

	wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));

	wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32);



	put_cpu();

}
@@ -2198,7 +2198,7 @@ static inline void setup_getcpu(int cpu) 
	struct desc_struct d = { };



	if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))

		wrmsr(MSR_TSC_AUX, cpudata, 0);

		wrmsrq(MSR_TSC_AUX, cpudata);



	/* Store CPU and node number in limit. */

	d.limit0 = cpudata;