Commit 44739490 authored by James Clark's avatar James Clark Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Update N2 and V2 metrics and events using Arm telemetry repo 

Apart from some slight naming and grouping differences, the new metrics
are functionally the same as the existing ones. Any missing metrics were
manually appended to the end of the auto generated file.

For the events, the new data includes descriptions that may have product
specific details and new groupings that will be consistent with other
products.

After generating the metrics from the telemetry repo [1], the following
manual steps were performed:

 * Change the topdown expressions to compare on CPUID and use
   #slots so that the same data can be shared between N2 and V2. Apart
   from these modifications, the expressions now match more closely with
   the Arm telemetry data which will hopefully make future updates
   easier.

 * Append some metrics from the old N2/V2 data that aren't present in
   the telemetry data. These will possibly be added to the
   telemetry-solution repo at a later time:

    l3d_cache_mpki, l3d_cache_miss_rate, branch_pki, ipc_rate, spec_ipc,
    retired_rate, wasted_rate, branch_immed_spec_rate,
    branch_return_spec_rate, branch_indirect_spec_rate

[1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/blob/main/data/pmu/cpu/neoverse/neoverse-n2.json



Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Reviewed-by: default avatarJohn Garry <john.g.garry@oracle.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Eduard Zingerman <eddyz87@gmail.com>
Cc: Haixin Yu <yuhaixin.yhx@linux.alibaba.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nick Forrington <nick.forrington@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Sohom Datta <sohomdatta1@gmail.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230816114841.1679234-7-james.clark@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent d43f5491

tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/branch.json

deleted100644 → 0
+0 −8
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/bus.json

+8 −10
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

        "ArchStdEvent": "BUS_ACCESS",

        "PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually."

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

        "ArchStdEvent": "BUS_CYCLES",

        "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES."

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

        "ArchStdEvent": "BUS_ACCESS_RD",

        "PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually."

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "CNT_CYCLES"

        "ArchStdEvent": "BUS_ACCESS_WR",

        "PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually."

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/cache.json

deleted100644 → 0
+0 −155
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L3D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L3D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "LL_CACHE_RD"

    },

    {

        "ArchStdEvent": "LL_CACHE_MISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_TLB_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_TLB_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_WR"

    },

    {

        "ArchStdEvent": "L3D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1I_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L2D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L3D_CACHE_LMISS_RD"

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json

+30 −15
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_TAKEN"

        "ArchStdEvent": "EXC_TAKEN",

        "PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally."

    },

    {

        "ArchStdEvent": "MEMORY_ERROR"

        "ArchStdEvent": "EXC_RETURN",

        "PublicDescription": "Counts any architecturally executed exception return instructions. Eg: AArch64: ERET"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

        "ArchStdEvent": "EXC_UNDEF",

        "PublicDescription": "Counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED. Attempting to execute instruction bit patterns that have not been allocated. Attempting to execute instructions when they are disabled. Attempting to execute instructions at an inappropriate Exception level. Attempting to execute an instruction when the value of PSTATE.IL is 1."

    },

    {

        "ArchStdEvent": "EXC_SVC"

        "ArchStdEvent": "EXC_SVC",

        "PublicDescription": "Counts SVC exceptions taken locally."

    },

    {

        "ArchStdEvent": "EXC_PABORT"

        "ArchStdEvent": "EXC_PABORT",

        "PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instruction Aborts."

    },

    {

        "ArchStdEvent": "EXC_DABORT"

        "ArchStdEvent": "EXC_DABORT",

        "PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, interrupts from the nSEI inputs and internally generated SErrors."

    },

    {

        "ArchStdEvent": "EXC_IRQ"

        "ArchStdEvent": "EXC_IRQ",

        "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are taken locally."

    },

    {

        "ArchStdEvent": "EXC_FIQ"

        "ArchStdEvent": "EXC_FIQ",

        "PublicDescription": "Counts FIQ exceptions including the virtual FIQs that are taken locally."

    },

    {

        "ArchStdEvent": "EXC_SMC"

        "ArchStdEvent": "EXC_SMC",

        "PublicDescription": "Counts SMC exceptions take to EL3."

    },

    {

        "ArchStdEvent": "EXC_HVC"

        "ArchStdEvent": "EXC_HVC",

        "PublicDescription": "Counts HVC exceptions taken to EL2."

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

        "ArchStdEvent": "EXC_TRAP_PABORT",

        "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC."

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

        "ArchStdEvent": "EXC_TRAP_DABORT",

        "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data Aborts or SError interrupts. Conditions that could cause those exceptions are:\n\n1. Attempting to read or write memory where the MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Interrupts from the SEI input.\n4. internally generated SErrors."

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

        "ArchStdEvent": "EXC_TRAP_OTHER",

        "PublicDescription": "Counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, data aborts, Instruction Aborts, or interrupts."

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

        "ArchStdEvent": "EXC_TRAP_IRQ",

        "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are not taken locally."

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

        "ArchStdEvent": "EXC_TRAP_FIQ",

        "PublicDescription": "Counts FIQs which are not taken locally but taken from EL0, EL1,\n or EL2 to EL3 (which would be the normal behavior for FIQs when not executing\n in EL3)."

    }

]

tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/fp_operation.json

0 → 100644
+22 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "FP_HP_SPEC",

        "PublicDescription": "Counts speculatively executed half precision floating point operations."

    },

    {

        "ArchStdEvent": "FP_SP_SPEC",

        "PublicDescription": "Counts speculatively executed single precision floating point operations."

    },

    {

        "ArchStdEvent": "FP_DP_SPEC",

        "PublicDescription": "Counts speculatively executed double precision floating point operations."

    },

    {

        "ArchStdEvent": "FP_SCALE_OPS_SPEC",

        "PublicDescription": "Counts speculatively executed scalable single precision floating point operations."

    },

    {

        "ArchStdEvent": "FP_FIXED_OPS_SPEC",

        "PublicDescription": "Counts speculatively executed non-scalable single precision floating point operations."

    }

]