Commit 448588ad authored by Marco Chiappero's avatar Marco Chiappero Committed by Herbert Xu
Browse files

crypto: qat - add the adf_get_pmisc_base() helper function 



Add and use the new helper function adf_get_pmisc_base() where convenient.

Also:
- remove no longer shared variables
- leverage other utilities, such as GET_PFVF_OPS(), as a consequence
- consistently use the "pmisc_addr" name for the returned value of this
  new helper

Signed-off-by: default avatarMarco Chiappero <marco.chiappero@intel.com>
Co-developed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 03125541

drivers/crypto/qat/qat_common/adf_admin.c

+4 −6
Original line number Diff line number Diff line
@@ -255,9 +255,7 @@ int adf_init_admin_comms(struct adf_accel_dev *accel_dev) 
{

	struct adf_admin_comms *admin;

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	struct adf_bar *pmisc =

		&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];

	void __iomem *csr = pmisc->virt_addr;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	struct admin_info admin_csrs_info;

	u32 mailbox_offset, adminmsg_u, adminmsg_l;

	void __iomem *mailbox;
@@ -291,13 +289,13 @@ int adf_init_admin_comms(struct adf_accel_dev *accel_dev) 
	hw_data->get_admin_info(&admin_csrs_info);



	mailbox_offset = admin_csrs_info.mailbox_offset;

	mailbox = csr + mailbox_offset;

	mailbox = pmisc_addr + mailbox_offset;

	adminmsg_u = admin_csrs_info.admin_msg_ur;

	adminmsg_l = admin_csrs_info.admin_msg_lr;



	reg_val = (u64)admin->phy_addr;

	ADF_CSR_WR(csr, adminmsg_u, upper_32_bits(reg_val));

	ADF_CSR_WR(csr, adminmsg_l, lower_32_bits(reg_val));

	ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val));

	ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val));



	mutex_init(&admin->lock);

	admin->mailbox_addr = mailbox;

drivers/crypto/qat/qat_common/adf_common_drv.h

+11 −0
Original line number Diff line number Diff line
@@ -243,4 +243,15 @@ static inline void adf_flush_vf_wq(struct adf_accel_dev *accel_dev) 
}



#endif



static inline void __iomem *adf_get_pmisc_base(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	struct adf_bar *pmisc;



	pmisc = &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];



	return pmisc->virt_addr;

}



#endif

drivers/crypto/qat/qat_common/adf_gen2_hw_data.c

+13 −26
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)

/* Copyright(c) 2020 Intel Corporation */

#include "adf_common_drv.h"

#include "adf_gen2_hw_data.h"

#include "icp_qat_hw.h"

#include <linux/pci.h>
@@ -25,31 +26,29 @@ EXPORT_SYMBOL_GPL(adf_gen2_get_num_aes); 
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	struct adf_bar *misc_bar = &GET_BARS(accel_dev)

					[hw_data->get_misc_bar_id(hw_data)];

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	unsigned long accel_mask = hw_data->accel_mask;

	unsigned long ae_mask = hw_data->ae_mask;

	void __iomem *csr = misc_bar->virt_addr;

	unsigned int val, i;



	/* Enable Accel Engine error detection & correction */

	for_each_set_bit(i, &ae_mask, hw_data->num_engines) {

		val = ADF_CSR_RD(csr, ADF_GEN2_AE_CTX_ENABLES(i));

		val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i));

		val |= ADF_GEN2_ENABLE_AE_ECC_ERR;

		ADF_CSR_WR(csr, ADF_GEN2_AE_CTX_ENABLES(i), val);

		val = ADF_CSR_RD(csr, ADF_GEN2_AE_MISC_CONTROL(i));

		ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val);

		val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i));

		val |= ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR;

		ADF_CSR_WR(csr, ADF_GEN2_AE_MISC_CONTROL(i), val);

		ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i), val);

	}



	/* Enable shared memory error detection & correction */

	for_each_set_bit(i, &accel_mask, hw_data->num_accel) {

		val = ADF_CSR_RD(csr, ADF_GEN2_UERRSSMSH(i));

		val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i));

		val |= ADF_GEN2_ERRSSMSH_EN;

		ADF_CSR_WR(csr, ADF_GEN2_UERRSSMSH(i), val);

		val = ADF_CSR_RD(csr, ADF_GEN2_CERRSSMSH(i));

		ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val);

		val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i));

		val |= ADF_GEN2_ERRSSMSH_EN;

		ADF_CSR_WR(csr, ADF_GEN2_CERRSSMSH(i), val);

		ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val);

	}

}

EXPORT_SYMBOL_GPL(adf_gen2_enable_error_correction);
@@ -57,15 +56,9 @@ EXPORT_SYMBOL_GPL(adf_gen2_enable_error_correction); 
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,

			   int num_a_regs, int num_b_regs)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	void __iomem *pmisc_addr;

	struct adf_bar *pmisc;

	int pmisc_id, i;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	u32 reg;



	pmisc_id = hw_data->get_misc_bar_id(hw_data);

	pmisc = &GET_BARS(accel_dev)[pmisc_id];

	pmisc_addr = pmisc->virt_addr;

	int i;



	/* Set/Unset Valid bit in AE Thread to PCIe Function Mapping Group A */

	for (i = 0; i < num_a_regs; i++) {
@@ -245,18 +238,12 @@ EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap); 
void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	u32 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;

	u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;

	unsigned long accel_mask = hw_data->accel_mask;

	void __iomem *pmisc_addr;

	struct adf_bar *pmisc;

	int pmisc_id;

	u32 i = 0;



	pmisc_id = hw_data->get_misc_bar_id(hw_data);

	pmisc = &GET_BARS(accel_dev)[pmisc_id];

	pmisc_addr = pmisc->virt_addr;



	/* Configures WDT timers */

	for_each_set_bit(i, &accel_mask, hw_data->num_accel) {

		/* Enable WDT for sym and dc */

drivers/crypto/qat/qat_common/adf_gen2_pfvf.c

+9 −15
Original line number Diff line number Diff line
@@ -75,15 +75,12 @@ static void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, 
static int adf_gen2_pfvf_send(struct adf_accel_dev *accel_dev, u32 msg,

			      u8 vf_nr)

{

	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	void __iomem *pmisc_bar_addr =

		pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr;

	u32 val, pfvf_offset, count = 0;

	u32 local_in_use_mask, local_in_use_pattern;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	unsigned int retries = ADF_PFVF_MSG_MAX_RETRIES;

	u32 remote_in_use_mask, remote_in_use_pattern;

	u32 local_in_use_mask, local_in_use_pattern;

	u32 val, pfvf_offset, count = 0;

	struct mutex *lock;	/* lock preventing concurrent acces of CSR */

	unsigned int retries = ADF_PFVF_MSG_MAX_RETRIES;

	u32 int_bit;

	int ret;
@@ -114,7 +111,7 @@ static int adf_gen2_pfvf_send(struct adf_accel_dev *accel_dev, u32 msg, 
	ret = 0;



	/* Check if the PFVF CSR is in use by remote function */

	val = ADF_CSR_RD(pmisc_bar_addr, pfvf_offset);

	val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

	if ((val & remote_in_use_mask) == remote_in_use_pattern) {

		dev_dbg(&GET_DEV(accel_dev),

			"PFVF CSR in use by remote function\n");
@@ -122,12 +119,12 @@ static int adf_gen2_pfvf_send(struct adf_accel_dev *accel_dev, u32 msg, 
	}



	/* Attempt to get ownership of the PFVF CSR */

	ADF_CSR_WR(pmisc_bar_addr, pfvf_offset, msg | int_bit);

	ADF_CSR_WR(pmisc_addr, pfvf_offset, msg | int_bit);



	/* Wait for confirmation from remote func it received the message */

	do {

		msleep(ADF_PFVF_MSG_ACK_DELAY);

		val = ADF_CSR_RD(pmisc_bar_addr, pfvf_offset);

		val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

	} while ((val & int_bit) && (count++ < ADF_PFVF_MSG_ACK_MAX_RETRY));



	if (val & int_bit) {
@@ -143,7 +140,7 @@ static int adf_gen2_pfvf_send(struct adf_accel_dev *accel_dev, u32 msg, 
	}



	/* Finished with the PFVF CSR; relinquish it and leave msg in CSR */

	ADF_CSR_WR(pmisc_bar_addr, pfvf_offset, val & ~local_in_use_mask);

	ADF_CSR_WR(pmisc_addr, pfvf_offset, val & ~local_in_use_mask);

out:

	mutex_unlock(lock);

	return ret;
@@ -160,10 +157,7 @@ static int adf_gen2_pfvf_send(struct adf_accel_dev *accel_dev, u32 msg, 


static u32 adf_gen2_pfvf_recv(struct adf_accel_dev *accel_dev, u8 vf_nr)

{

	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	void __iomem *pmisc_addr =

		pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	u32 pfvf_offset;

	u32 msg_origin;

	u32 int_bit;

drivers/crypto/qat/qat_common/adf_gen4_hw_data.c

+1 −8
Original line number Diff line number Diff line
@@ -111,20 +111,13 @@ static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, 


void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;

	u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;

	u32 ssm_wdt_pke_high = 0;

	u32 ssm_wdt_pke_low = 0;

	u32 ssm_wdt_high = 0;

	u32 ssm_wdt_low = 0;

	void __iomem *pmisc_addr;

	struct adf_bar *pmisc;

	int pmisc_id;



	pmisc_id = hw_data->get_misc_bar_id(hw_data);

	pmisc = &GET_BARS(accel_dev)[pmisc_id];

	pmisc_addr = pmisc->virt_addr;



	/* Convert 64bit WDT timer value into 32bit values for

	 * mmio write to 32bit CSRs.