Commit 448f828f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 perf fixes from Borislav Petkov:

 - Define the correct set of default hw events on AMD Zen4

 - Use the correct stalled cycles PMCs on AMD Zen2 and newer

 - Fix detection of the LBR freeze feature on AMD

* tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later
  perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later
  perf/x86/amd/lbr: Use freeze based on availability
  x86/cpufeatures: Add new word for scattered features
parents 8d338df7 68cdf1e6

arch/x86/events/amd/core.c

+34 −5
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = 
/*

 * AMD Performance Monitor Family 17h and later:

 */

static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =

static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -262,10 +262,39 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = 
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x0187,

};



static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,

};



static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,

	[PERF_COUNT_HW_REF_CPU_CYCLES]		= 0x100000120,

};



static u64 amd_pmu_event_map(int hw_event)

{

	if (boot_cpu_data.x86 >= 0x17)

		return amd_f17h_perfmon_event_map[hw_event];

	if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)

		return amd_zen4_perfmon_event_map[hw_event];



	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)

		return amd_zen2_perfmon_event_map[hw_event];



	if (cpu_feature_enabled(X86_FEATURE_ZEN1))

		return amd_zen1_perfmon_event_map[hw_event];



	return amd_perfmon_event_map[hw_event];

}
@@ -904,8 +933,8 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) 
	if (!status)

		goto done;



	/* Read branch records before unfreezing */

	if (status & GLOBAL_STATUS_LBRS_FROZEN) {

	/* Read branch records */

	if (x86_pmu.lbr_nr) {

		amd_pmu_lbr_read();

		status &= ~GLOBAL_STATUS_LBRS_FROZEN;

	}

arch/x86/events/amd/lbr.c

+10 −6
Original line number Diff line number Diff line
@@ -402,10 +402,12 @@ void amd_pmu_lbr_enable_all(void) 
		wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select);

	}



	if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {

		rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);

	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);



		wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

	}



	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);

	wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);

}
@@ -418,11 +420,13 @@ void amd_pmu_lbr_disable_all(void) 
		return;



	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);

	rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);



	wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);



	if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {

		rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);

		wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

	}

}



__init int amd_pmu_lbr_init(void)

{

arch/x86/include/asm/cpufeature.h

+4 −2
Original line number Diff line number Diff line
@@ -91,8 +91,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 21))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 22))



#define DISABLED_MASK_BIT_SET(feature_bit)				\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\
@@ -116,8 +117,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 21))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 22))



#define cpu_has(c, bit)							\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\

arch/x86/include/asm/cpufeatures.h

+9 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS			21	   /* N 32-bit words worth of info */

#define NCAPINTS			22	   /* N 32-bit words worth of info */

#define NBUGINTS			2	   /* N 32-bit bug flags */



/*
@@ -459,6 +459,14 @@ 
#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */

#define X86_FEATURE_SRSO_NO		(20*32+29) /* "" CPU is not affected by SRSO */



/*

 * Extended auxiliary flags: Linux defined - for features scattered in various

 * CPUID levels like 0x80000022, etc.

 *

 * Reuse free bits when adding new feature flags!

 */

#define X86_FEATURE_AMD_LBR_PMC_FREEZE	(21*32+ 0) /* AMD LBR and PMC Freeze */



/*

 * BUG word(s)

 */

arch/x86/include/asm/disabled-features.h

+2 −1
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ 
#define DISABLED_MASK18	(DISABLE_IBT)

#define DISABLED_MASK19	(DISABLE_SEV_SNP)

#define DISABLED_MASK20	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)

#define DISABLED_MASK21	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)



#endif /* _ASM_X86_DISABLED_FEATURES_H */