Commit 44a88fa4 authored by Connor Abbott's avatar Connor Abbott Committed by Rob Clark
Browse files

drm/msm: Add param for the highest bank bit 



This parameter is programmed by the kernel and influences the tiling
layout of images. Exposing it to userspace will allow it to tile/untile
images correctly without guessing what value the kernel programmed, and
allow us to change it in the future without breaking userspace.

Signed-off-by: default avatarConnor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/571181/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 8814455a

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+3 −0
Original line number Diff line number Diff line
@@ -373,6 +373,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 
			return -EINVAL;

		*value = ctx->aspace->va_size;

		return 0;

	case MSM_PARAM_HIGHEST_BANK_BIT:

		*value = adreno_gpu->ubwc_config.highest_bank_bit;

		return 0;

	default:

		DBG("%s: invalid param: %u", gpu->name, param);

		return -EINVAL;

include/uapi/drm/msm_drm.h

+1 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ struct drm_msm_timespec { 
#define MSM_PARAM_CMDLINE    0x0d  /* WO: override for task cmdline */

#define MSM_PARAM_VA_START   0x0e  /* RO: start of valid GPU iova range */

#define MSM_PARAM_VA_SIZE    0x0f  /* RO: size of valid GPU iova range (bytes) */

#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */



/* For backwards compat.  The original support for preemption was based on

 * a single ring per priority level so # of priority levels equals the #