Commit 44b305a2 authored by Wadim Mueller's avatar Wadim Mueller Committed by Shawn Guo
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arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3 

This commit adds device tree support for the NXP S32G3-based
S32G-VNP-RDB3 Board [1].

The S32G3 features an 8-core ARM Cortex-A53 based SoC developed by NXP.

The device tree files are derived from the official NXP downstream
Linux tree [2].

This addition encompasses a limited selection of peripherals that
are upstream-supported. Apart from the ARM System Modules
(GIC, Generic Timer, etc.), the following IPs have been validated:

    * UART: fsl-linflexuart
    * SDHC: fsl-imx-esdhc

Clock settings for the chip rely on ATF Firmware [3].
Pin control integration into the device tree is pending and currently
relies on Firmware/U-Boot settings [4].

These changes were validated using BSP39 Firmware/U-Boot from NXP [5].

The modifications enable booting the official Ubuntu 22.04 from NXP on
the RDB3 with default settings from the SD card and eMMC.

[1] https://www.nxp.com/design/design-center/designs/s32g3-vehicle-networking-reference-design:S32G-VNP-RDB3
[2] https://github.com/nxp-auto-linux/linux
[3] https://github.com/nxp-auto-linux/arm-trusted-firmware
[4] https://github.com/nxp-auto-linux/u-boot
[5] https://github.com/nxp-auto-linux/auto_yocto_bsp



Signed-off-by: default avatarWadim Mueller <wafgo01@gmail.com>
Tested-by: default avatarGhennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
Reviewed-by: default avatarGhennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b98807c7

arch/arm64/boot/dts/freescale/Makefile

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@@ -259,4 +259,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb 


dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb

dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb

dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb

dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

arch/arm64/boot/dts/freescale/s32g3.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright 2021-2023 NXP

 *

 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

 *          Ciprian Costea <ciprianmarian.costea@nxp.com>

 *          Andra-Teodora Ilie <andra.ilie@nxp.com>

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "nxp,s32g3";

	interrupt-parent = <&gic>;

	#address-cells = <0x02>;

	#size-cells = <0x02>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0>;

				};



				core1 {

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&cpu3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu4>;

				};



				core1 {

					cpu = <&cpu5>;

				};



				core2 {

					cpu = <&cpu6>;

				};



				core3 {

					cpu = <&cpu7>;

				};

			};

		};



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};



		cpu7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "psci";

			clocks = <&dfs 0>;

		};

	};



	firmware {

		scmi: scmi {

			compatible = "arm,scmi-smc";

			shmem = <&scmi_shmem>;

			arm,smc-id = <0xc20000fe>;

			#address-cells = <1>;

			#size-cells = <0>;



			dfs: protocol@13 {

				reg = <0x13>;

				#clock-cells = <1>;

			};



			clks: protocol@14 {

				reg = <0x14>;

				#clock-cells = <1>;

			};

		};



		psci: psci {

			compatible = "arm,psci-1.0";

			method = "smc";

		};

	};





	pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};



	reserved-memory  {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		scmi_shmem: shm@d0000000 {

			compatible = "arm,scmi-shmem";

			reg = <0x0 0xd0000000 0x0 0x80>;

			no-map;

		};

	};



	soc@0 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0x80000000>;



		uart0: serial@401c8000 {

			compatible = "nxp,s32g3-linflexuart",

				     "fsl,s32v234-linflexuart";

			reg = <0x401c8000 0x3000>;

			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;

			status = "disabled";

		};



		uart1: serial@401cc000 {

			compatible = "nxp,s32g3-linflexuart",

				     "fsl,s32v234-linflexuart";

			reg = <0x401cc000 0x3000>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;

			status = "disabled";

		};



		uart2: serial@402bc000 {

			compatible = "nxp,s32g3-linflexuart",

				     "fsl,s32v234-linflexuart";

			reg = <0x402bc000 0x3000>;

			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;

			status = "disabled";

		};



		usdhc0: mmc@402f0000 {

			compatible = "nxp,s32g3-usdhc",

				     "nxp,s32g2-usdhc";

			reg = <0x402f0000 0x1000>;

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clks 32>,

				 <&clks 31>,

				 <&clks 33>;

			clock-names = "ipg", "ahb", "per";

			status = "disabled";

		};



		gic: interrupt-controller@50800000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x50800000 0x10000>,

			      <0x50900000 0x200000>,

			      <0x50400000 0x2000>,

			      <0x50410000 0x2000>,

			      <0x50420000 0x2000>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */

			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */

		arm,no-tick-in-suspend;

	};

};

arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright 2021-2023 NXP

 *

 * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)

 */



/dts-v1/;



#include "s32g3.dtsi"



/ {

	model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";

	compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";



	aliases {

		mmc0 = &usdhc0;

		serial0 = &uart0;

		serial1 = &uart1;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	/* 4GiB RAM */

	memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0 0x80000000>,

		      <0x8 0x80000000 0 0x80000000>;

	};

};



&uart0 {

	status = "okay";

};



&uart1 {

	status = "okay";

};



&usdhc0 {

	bus-width = <8>;

	status = "okay";

};