Commit 44f392fb authored by Alex Deucher's avatar Alex Deucher
Browse files

Revert "drm/amd/pm: correct the workload setting" 

This reverts commit 74e10064.

This causes a regression in the workload selection.
A more extensive fix is being worked on.
For now, revert.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3618


Fixes: 74e10064 ("drm/amd/pm: correct the workload setting")
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7013a826

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+14 −35
Original line number Diff line number Diff line
@@ -1259,33 +1259,26 @@ static int smu_sw_init(void *handle) 
	smu->watermarks_bitmap = 0;

	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

	smu->user_dpm_profile.user_workload_mask = 0;



	atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);

	atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);

	atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);

	atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);



	smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;

	smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;

	smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;

	smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3;

	smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4;

	smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;

	smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;

	smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;

	smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;

	smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;

	smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;

	smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;

	smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;

	smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;



	if (smu->is_apu ||

	    !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) {

		smu->driver_workload_mask =

			1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];

	} else {

		smu->driver_workload_mask =

			1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];

		smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;

	}

	    !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D))

		smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];

	else

		smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];



	smu->workload_mask = smu->driver_workload_mask |

							smu->user_dpm_profile.user_workload_mask;

	smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

	smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;

	smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
@@ -2355,20 +2348,17 @@ static int smu_switch_power_profile(void *handle, 
		return -EINVAL;



	if (!en) {

		smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]);

		smu->workload_mask &= ~(1 << smu->workload_prority[type]);

		index = fls(smu->workload_mask);

		index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;

		workload[0] = smu->workload_setting[index];

	} else {

		smu->driver_workload_mask |= (1 << smu->workload_priority[type]);

		smu->workload_mask |= (1 << smu->workload_prority[type]);

		index = fls(smu->workload_mask);

		index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;

		workload[0] = smu->workload_setting[index];

	}



	smu->workload_mask = smu->driver_workload_mask |

						 smu->user_dpm_profile.user_workload_mask;



	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&

		smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)

		smu_bump_power_profile_mode(smu, workload, 0);
@@ -3059,23 +3049,12 @@ static int smu_set_power_profile_mode(void *handle, 
				      uint32_t param_size)

{

	struct smu_context *smu = handle;

	int ret;



	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||

	    !smu->ppt_funcs->set_power_profile_mode)

		return -EOPNOTSUPP;



	if (smu->user_dpm_profile.user_workload_mask &

	   (1 << smu->workload_priority[param[param_size]]))

	   return 0;



	smu->user_dpm_profile.user_workload_mask =

		(1 << smu->workload_priority[param[param_size]]);

	smu->workload_mask = smu->user_dpm_profile.user_workload_mask |

		smu->driver_workload_mask;

	ret = smu_bump_power_profile_mode(smu, param, param_size);



	return ret;

	return smu_bump_power_profile_mode(smu, param, param_size);

}



static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+1 −3
Original line number Diff line number Diff line
@@ -240,7 +240,6 @@ struct smu_user_dpm_profile { 
	/* user clock state information */

	uint32_t clk_mask[SMU_CLK_COUNT];

	uint32_t clk_dependency;

	uint32_t user_workload_mask;

};



#define SMU_TABLE_INIT(tables, table_id, s, a, d)	\
@@ -558,8 +557,7 @@ struct smu_context { 
	bool disable_uclk_switch;



	uint32_t workload_mask;

	uint32_t driver_workload_mask;

	uint32_t workload_priority[WORKLOAD_POLICY_MAX];

	uint32_t workload_prority[WORKLOAD_POLICY_MAX];

	uint32_t workload_setting[WORKLOAD_POLICY_MAX];

	uint32_t power_profile_mode;

	uint32_t default_power_profile_mode;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+3 −2
Original line number Diff line number Diff line
@@ -1455,6 +1455,7 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, 
		return -EINVAL;

	}





	if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&

	     (smu->smc_fw_version >= 0x360d00)) {

		if (size != 10)
@@ -1522,14 +1523,14 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, 


	ret = smu_cmn_send_smc_msg_with_param(smu,

					  SMU_MSG_SetWorkloadMask,

					  smu->workload_mask,

					  1 << workload_type,

					  NULL);

	if (ret) {

		dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);

		return ret;

	}



	smu_cmn_assign_power_profile(smu);

	smu->power_profile_mode = profile_mode;



	return 0;

}

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+1 −4
Original line number Diff line number Diff line
@@ -2081,13 +2081,10 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u 
						       smu->power_profile_mode);

	if (workload_type < 0)

		return -EINVAL;



	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,

				    smu->workload_mask, NULL);

				    1 << workload_type, NULL);

	if (ret)

		dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);

	else

		smu_cmn_assign_power_profile(smu);



	return ret;

}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+1 −4
Original line number Diff line number Diff line
@@ -1786,13 +1786,10 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * 
						       smu->power_profile_mode);

	if (workload_type < 0)

		return -EINVAL;



	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,

				    smu->workload_mask, NULL);

				    1 << workload_type, NULL);

	if (ret)

		dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);

	else

		smu_cmn_assign_power_profile(smu);



	return ret;

}