Commit 44f90d7c authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'microchip_t1s-update-on-microchip-10base-t1s-phy-driver' 

Parthiban Veerasooran says:

====================
microchip_t1s: Update on Microchip 10BASE-T1S PHY driver

This patch series contain the below updates:
- Restructured lan865x_write_cfg_params() and lan865x_read_cfg_params()
  functions arguments to more generic.
- Updated new/improved initial settings of LAN865X Rev.B0 from latest
  AN1760.
- Added support for LAN865X Rev.B1 from latest AN1760.
- Moved LAN867X reset handling to a new function for flexibility.
- Added support for LAN867X Rev.C1/C2 from latest AN1699.
- Disabled/enabled collision detection based on PLCA setting.
====================

Link: https://patch.msgid.link/20241010082205.221493-1-parthiban.veerasooran@microchip.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents ec35b0c5 78341049

drivers/net/phy/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -292,8 +292,8 @@ config MICREL_PHY 
config MICROCHIP_T1S_PHY

	tristate "Microchip 10BASE-T1S Ethernet PHYs"

	help

	  Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0 Internal

	  PHYs.

	  Currently supports the LAN8670/1/2 Rev.B1/C1/C2 and

	  LAN8650/1 Rev.B0/B1 Internal PHYs.



config MICROCHIP_PHY

	tristate "Microchip PHYs"

drivers/net/phy/microchip_t1s.c

+238 −62
Original line number Diff line number Diff line
@@ -3,8 +3,8 @@ 
 * Driver for Microchip 10BASE-T1S PHYs

 *

 * Support: Microchip Phys:

 *  lan8670/1/2 Rev.B1

 *  lan8650/1 Rev.B0 Internal PHYs

 *  lan8670/1/2 Rev.B1/C1/C2

 *  lan8650/1 Rev.B0/B1 Internal PHYs

 */



#include <linux/kernel.h>
@@ -12,7 +12,10 @@ 
#include <linux/phy.h>



#define PHY_ID_LAN867X_REVB1 0x0007C162

#define PHY_ID_LAN865X_REVB0 0x0007C1B3

#define PHY_ID_LAN867X_REVC1 0x0007C164

#define PHY_ID_LAN867X_REVC2 0x0007C165

/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */

#define PHY_ID_LAN865X_REVB 0x0007C1B3



#define LAN867X_REG_STS2 0x0019
@@ -23,6 +26,12 @@ 
#define LAN865X_REG_CFGPARAM_CTRL 0x00DA

#define LAN865X_REG_STS2 0x0019



/* Collision Detector Control 0 Register */

#define LAN86XX_REG_COL_DET_CTRL0	0x0087

#define COL_DET_CTRL0_ENABLE_BIT_MASK	BIT(15)

#define COL_DET_ENABLE			BIT(15)

#define COL_DET_DISABLE			0x0000



#define LAN865X_CFGPARAM_READ_ENABLE BIT(1)



/* The arrays below are pulled from the following table from AN1699
@@ -59,29 +68,45 @@ static const u16 lan867x_revb1_fixup_masks[12] = { 
	0x0600, 0x7F00, 0x2000, 0xFFFF,

};



/* LAN865x Rev.B0 configuration parameters from AN1760 */

static const u32 lan865x_revb0_fixup_registers[28] = {

	0x0091, 0x0081, 0x0043, 0x0044,

	0x0045, 0x0053, 0x0054, 0x0055,

	0x0040, 0x0050, 0x00D0, 0x00E9,

	0x00F5, 0x00F4, 0x00F8, 0x00F9,

/* LAN865x Rev.B0/B1 configuration parameters from AN1760

 * As per the Configuration Application Note AN1760 published in the below link,

 * https://www.microchip.com/en-us/application-notes/an1760

 * Revision F (DS60001760G - June 2024)

 */

static const u32 lan865x_revb_fixup_registers[17] = {

	0x00D0, 0x00E0, 0x00E9, 0x00F5,

	0x00F4, 0x00F8, 0x00F9, 0x0081,

	0x0091, 0x0043, 0x0044, 0x0045,

	0x0053, 0x0054, 0x0055, 0x0040,

	0x0050,

};



static const u16 lan865x_revb_fixup_values[17] = {

	0x3F31, 0xC000, 0x9E50, 0x1CF8,

	0xC020, 0xB900, 0x4E53, 0x0080,

	0x9660, 0x00FF, 0xFFFF, 0x0000,

	0x00FF, 0xFFFF, 0x0000, 0x0002,

	0x0002,

};



static const u16 lan865x_revb_fixup_cfg_regs[2] = {

	0x0084, 0x008A,

};



static const u32 lan865x_revb_sqi_fixup_regs[12] = {

	0x00B0, 0x00B1, 0x00B2, 0x00B3,

	0x00B4, 0x00B5, 0x00B6, 0x00B7,

	0x00B8, 0x00B9, 0x00BA, 0x00BB,

};



static const u16 lan865x_revb0_fixup_values[28] = {

	0x9660, 0x00C0, 0x00FF, 0xFFFF,

	0x0000, 0x00FF, 0xFFFF, 0x0000,

	0x0002, 0x0002, 0x5F21, 0x9E50,

	0x1CF8, 0xC020, 0x9B00, 0x4E53,

static const u16 lan865x_revb_sqi_fixup_values[12] = {

	0x0103, 0x0910, 0x1D26, 0x002A,

	0x0103, 0x070D, 0x1720, 0x0027,

	0x0509, 0x0E13, 0x1C25, 0x002B,

};



static const u16 lan865x_revb0_fixup_cfg_regs[5] = {

	0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF

static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] = {

	0x00AD, 0x00AE, 0x00AF,

};



/* Pulled from AN1760 describing 'indirect read'
@@ -92,7 +117,7 @@ static const u16 lan865x_revb0_fixup_cfg_regs[5] = { 
 *

 * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2

 */

static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr)

static int lan865x_revb_indirect_read(struct phy_device *phydev, u16 addr)

{

	int ret;
@@ -112,15 +137,18 @@ static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr) 
/* This is pulled straight from AN1760 from 'calculation of offset 1' &

 * 'calculation of offset 2'

 */

static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2])

static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[])

{

	const u16 fixup_regs[2] = {0x0004, 0x0008};

	int ret;



	for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {

		ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]);

		ret = lan865x_revb_indirect_read(phydev, fixup_regs[i]);

		if (ret < 0)

			return ret;



		/* 5-bit signed value, sign extend */

		ret &= GENMASK(4, 0);

		if (ret & BIT(4))

			offsets[i] = ret | 0xE0;

		else
@@ -130,13 +158,15 @@ static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2] 
	return 0;

}



static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[])

static int lan865x_read_cfg_params(struct phy_device *phydev,

				   const u16 cfg_regs[], u16 cfg_params[],

				   u8 count)

{

	int ret;



	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {

	for (int i = 0; i < count; i++) {

		ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,

				   lan865x_revb0_fixup_cfg_regs[i]);

				   cfg_regs[i]);

		if (ret < 0)

			return ret;

		cfg_params[i] = (u16)ret;
@@ -145,13 +175,14 @@ static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[]) 
	return 0;

}



static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[])

static int lan865x_write_cfg_params(struct phy_device *phydev,

				    const u16 cfg_regs[], u16 cfg_params[],

				    u8 count)

{

	int ret;



	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,

				    lan865x_revb0_fixup_cfg_regs[i],

	for (int i = 0; i < count; i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i],

				    cfg_params[i]);

		if (ret)

			return ret;
@@ -160,60 +191,90 @@ static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[]) 
	return 0;

}



static int lan865x_setup_cfgparam(struct phy_device *phydev)

static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[])

{

	u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)];

	u16 cfg_results[5];

	s8 offsets[2];

	u16 cfg_results[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];

	u16 cfg_params[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];

	int ret;



	ret = lan865x_generate_cfg_offsets(phydev, offsets);

	ret = lan865x_read_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,

				      cfg_params, ARRAY_SIZE(cfg_params));

	if (ret)

		return ret;



	ret = lan865x_read_cfg_params(phydev, cfg_params);

	cfg_results[0] = FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |

			 FIELD_PREP(GENMASK(9, 4), 14 + offsets[0]) |

			 0x03;

	cfg_results[1] = FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);



	return lan865x_write_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,

					cfg_results, ARRAY_SIZE(cfg_results));

}



static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[])

{

	u16 cfg_results[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];

	u16 cfg_params[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];

	int ret;



	ret = lan865x_read_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,

				      cfg_params, ARRAY_SIZE(cfg_params));

	if (ret)

		return ret;



	cfg_results[0] = (cfg_params[0] & 0x000F) |

			  FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |

			  FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]);

	cfg_results[1] = (cfg_params[1] & 0x03FF) |

			  FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);

	cfg_results[2] = (cfg_params[2] & 0xC0C0) |

			  FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) |

	cfg_results[0] = FIELD_PREP(GENMASK(13, 8), 5 + offsets[0]) |

			 (9 + offsets[0]);

	cfg_results[3] = (cfg_params[3] & 0xC0C0) |

			  FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) |

	cfg_results[1] = FIELD_PREP(GENMASK(13, 8), 9 + offsets[0]) |

			 (14 + offsets[0]);

	cfg_results[4] = (cfg_params[4] & 0xC0C0) |

			  FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) |

	cfg_results[2] = FIELD_PREP(GENMASK(13, 8), 17 + offsets[0]) |

			 (22 + offsets[0]);



	return lan865x_write_cfg_params(phydev, cfg_results);

	return lan865x_write_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,

					cfg_results, ARRAY_SIZE(cfg_results));

}



static int lan865x_revb0_config_init(struct phy_device *phydev)

static int lan865x_revb_config_init(struct phy_device *phydev)

{

	s8 offsets[2];

	int ret;



	/* Reference to AN1760

	 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf

	 */

	for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) {

	ret = lan865x_generate_cfg_offsets(phydev, offsets);

	if (ret)

		return ret;



	for (int i = 0; i < ARRAY_SIZE(lan865x_revb_fixup_registers); i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,

				    lan865x_revb0_fixup_registers[i],

				    lan865x_revb0_fixup_values[i]);

				    lan865x_revb_fixup_registers[i],

				    lan865x_revb_fixup_values[i]);

		if (ret)

			return ret;



		if (i == 1) {

			ret = lan865x_setup_cfgparam(phydev, offsets);

			if (ret)

				return ret;

		}

	/* Function to calculate and write the configuration parameters in the

	 * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760)

	 */

	return lan865x_setup_cfgparam(phydev);

	}



static int lan867x_revb1_config_init(struct phy_device *phydev)

	ret = lan865x_setup_sqi_cfgparam(phydev, offsets);

	if (ret)

		return ret;



	for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,

				    lan865x_revb_sqi_fixup_regs[i],

				    lan865x_revb_sqi_fixup_values[i]);

		if (ret)

			return ret;

	}



	return 0;

}



static int lan867x_check_reset_complete(struct phy_device *phydev)

{

	int err;
@@ -235,6 +296,69 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) 
		}

	}



	return 0;

}



static int lan867x_revc_config_init(struct phy_device *phydev)

{

	s8 offsets[2];

	int ret;



	ret = lan867x_check_reset_complete(phydev);

	if (ret)

		return ret;



	ret = lan865x_generate_cfg_offsets(phydev, offsets);

	if (ret)

		return ret;



	/* LAN867x Rev.C1/C2 configuration settings are equal to the first 9

	 * configuration settings and all the sqi fixup settings from LAN865x

	 * Rev.B0/B1. So the same fixup registers and values from LAN865x

	 * Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication.

	 * Refer the below links for the comparison.

	 * https://www.microchip.com/en-us/application-notes/an1760

	 * Revision F (DS60001760G - June 2024)

	 * https://www.microchip.com/en-us/application-notes/an1699

	 * Revision E (DS60001699F - June 2024)

	 */

	for (int i = 0; i < 9; i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,

				    lan865x_revb_fixup_registers[i],

				    lan865x_revb_fixup_values[i]);

		if (ret)

			return ret;



		if (i == 1) {

			ret = lan865x_setup_cfgparam(phydev, offsets);

			if (ret)

				return ret;

		}

	}



	ret = lan865x_setup_sqi_cfgparam(phydev, offsets);

	if (ret)

		return ret;



	for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) {

		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,

				    lan865x_revb_sqi_fixup_regs[i],

				    lan865x_revb_sqi_fixup_values[i]);

		if (ret)

			return ret;

	}



	return 0;

}



static int lan867x_revb1_config_init(struct phy_device *phydev)

{

	int err;



	err = lan867x_check_reset_complete(phydev);

	if (err)

		return err;



	/* Reference to AN1699

	 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf

	 * AN1699 says Read, Modify, Write, but the Write is not required if the
@@ -253,6 +377,36 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) 
	return 0;

}



/* As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and

 * LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under

 * normal operation, the device should be operated in PLCA mode. Disabling

 * collision detection is recommended to allow the device to operate in noisy

 * environments or when reflections and other inherent transmission line

 * distortion cause poor signal quality. Collision detection must be re-enabled

 * if the device is configured to operate in CSMA/CD mode.

 *

 * AN1760: https://www.microchip.com/en-us/application-notes/an1760

 * AN1699: https://www.microchip.com/en-us/application-notes/an1699

 */

static int lan86xx_plca_set_cfg(struct phy_device *phydev,

				const struct phy_plca_cfg *plca_cfg)

{

	int ret;



	ret = genphy_c45_plca_set_cfg(phydev, plca_cfg);

	if (ret)

		return ret;



	if (plca_cfg->enabled)

		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,

				      LAN86XX_REG_COL_DET_CTRL0,

				      COL_DET_CTRL0_ENABLE_BIT_MASK,

				      COL_DET_DISABLE);



	return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0,

			      COL_DET_CTRL0_ENABLE_BIT_MASK, COL_DET_ENABLE);

}



static int lan86xx_read_status(struct phy_device *phydev)

{

	/* The phy has some limitations, namely:
@@ -308,15 +462,35 @@ static struct phy_driver microchip_t1s_driver[] = { 
		.get_plca_status    = genphy_c45_plca_get_status,

	},

	{

		PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0),

		.name               = "LAN865X Rev.B0 Internal Phy",

		PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1),

		.name               = "LAN867X Rev.C1",

		.features           = PHY_BASIC_T1S_P2MP_FEATURES,

		.config_init        = lan865x_revb0_config_init,

		.config_init        = lan867x_revc_config_init,

		.read_status        = lan86xx_read_status,

		.get_plca_cfg	    = genphy_c45_plca_get_cfg,

		.set_plca_cfg	    = lan86xx_plca_set_cfg,

		.get_plca_status    = genphy_c45_plca_get_status,

	},

	{

		PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2),

		.name               = "LAN867X Rev.C2",

		.features           = PHY_BASIC_T1S_P2MP_FEATURES,

		.config_init        = lan867x_revc_config_init,

		.read_status        = lan86xx_read_status,

		.get_plca_cfg	    = genphy_c45_plca_get_cfg,

		.set_plca_cfg	    = lan86xx_plca_set_cfg,

		.get_plca_status    = genphy_c45_plca_get_status,

	},

	{

		PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB),

		.name               = "LAN865X Rev.B0/B1 Internal Phy",

		.features           = PHY_BASIC_T1S_P2MP_FEATURES,

		.config_init        = lan865x_revb_config_init,

		.read_status        = lan86xx_read_status,

		.read_mmd           = lan865x_phy_read_mmd,

		.write_mmd          = lan865x_phy_write_mmd,

		.get_plca_cfg	    = genphy_c45_plca_get_cfg,

		.set_plca_cfg	    = genphy_c45_plca_set_cfg,

		.set_plca_cfg	    = lan86xx_plca_set_cfg,

		.get_plca_status    = genphy_c45_plca_get_status,

	},

};
@@ -325,7 +499,9 @@ module_phy_driver(microchip_t1s_driver); 


static struct mdio_device_id __maybe_unused tbl[] = {

	{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },

	{ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) },

	{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) },

	{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2) },

	{ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) },

	{ }

};