Commit 4523be8e authored by Frieder Schrempf's avatar Frieder Schrempf Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core 



According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 01df28d8

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+31 −0
Original line number Diff line number Diff line
@@ -1139,6 +1139,37 @@ gpmi: nand-controller@33002000{ 
			status = "disabled";

		};



		gpu_3d: gpu@38000000 {

			compatible = "vivante,gc";

			reg = <0x38000000 0x8000>;

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk IMX8MM_CLK_GPU_AHB>,

				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,

				 <&clk IMX8MM_CLK_GPU3D_ROOT>,

				 <&clk IMX8MM_CLK_GPU3D_ROOT>;

			clock-names = "reg", "bus", "core", "shader";

			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,

					  <&clk IMX8MM_GPU_PLL_OUT>;

			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;

			assigned-clock-rates = <0>, <1000000000>;

			power-domains = <&pgc_gpu>;

		};



		gpu_2d: gpu@38008000 {

			compatible = "vivante,gc";

			reg = <0x38008000 0x8000>;

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk IMX8MM_CLK_GPU_AHB>,

				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,

				 <&clk IMX8MM_CLK_GPU2D_ROOT>;

			clock-names = "reg", "bus", "core";

			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,

					  <&clk IMX8MM_GPU_PLL_OUT>;

			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;

			assigned-clock-rates = <0>, <1000000000>;

			power-domains = <&pgc_gpu>;

		};



		gic: interrupt-controller@38800000 {

			compatible = "arm,gic-v3";

			reg = <0x38800000 0x10000>, /* GIC Dist */