Commit 453805f0 authored by Clément Léger's avatar Clément Léger Committed by Alexandre Ghiti
Browse files

riscv: misaligned: enable IRQs while handling misaligned accesses 



We can safely reenable IRQs if coming from userspace. This allows to
access user memory that could potentially trigger a page fault.

Fixes: b686ecde ("riscv: misaligned: Restrict user access to kernel memory")
Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250422162324.956065-3-cleger@rivosinc.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parent fd94de9f

arch/riscv/kernel/traps.c

+8 −4
Original line number Diff line number Diff line
@@ -220,20 +220,24 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type 
{

	irqentry_state_t state;



	if (user_mode(regs))

	if (user_mode(regs)) {

		irqentry_enter_from_user_mode(regs);

	else

		local_irq_enable();

	} else {

		state = irqentry_nmi_enter(regs);

	}



	if (misaligned_handler[type].handler(regs))

		do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,

			      misaligned_handler[type].type_str);



	if (user_mode(regs))

	if (user_mode(regs)) {

		local_irq_disable();

		irqentry_exit_to_user_mode(regs);

	else

	} else {

		irqentry_nmi_exit(regs, state);

	}

}



asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)

{