Commit 4538480b authored by Amit Vadhavana's avatar Amit Vadhavana Committed by Jonathan Corbet
Browse files

Documentation: Fix spelling mistakes 



Correct spelling mistakes in the documentation to improve readability.

Signed-off-by: default avatarAmit Vadhavana <av2082000@gmail.com>
Reviewed-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20240817072724.6861-1-av2082000@gmail.com
parent 4a93831d

Documentation/arch/arm/stm32/stm32-dma-mdma-chaining.rst

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@@ -359,7 +359,7 @@ Driver updates for STM32 DMA-MDMA chaining support in foo driver 
    descriptor you want a callback to be called at the end of the transfer

    (dmaengine_prep_slave_sg()) or the period (dmaengine_prep_dma_cyclic()).

    Depending on the direction, set the callback on the descriptor that finishes

    the overal transfer:

    the overall transfer:



    * DMA_DEV_TO_MEM: set the callback on the "MDMA" descriptor

    * DMA_MEM_TO_DEV: set the callback on the "DMA" descriptor
@@ -371,7 +371,7 @@ Driver updates for STM32 DMA-MDMA chaining support in foo driver 
  As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue

  STM32 MDMA channel before STM32 DMA channel.



  If any, your callback will be called to warn you about the end of the overal

  If any, your callback will be called to warn you about the end of the overall

  transfer or the period completion.



  Don't forget to terminate both channels. STM32 DMA channel is configured in

Documentation/arch/arm64/cpu-hotplug.rst

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@@ -26,7 +26,7 @@ There are no systems that support the physical addition (or removal) of CPUs 
while the system is running, and ACPI is not able to sufficiently describe

them.



e.g. New CPUs come with new caches, but the platform's cache toplogy is

e.g. New CPUs come with new caches, but the platform's cache topology is

described in a static table, the PPTT. How caches are shared between CPUs is

not discoverable, and must be described by firmware.

Documentation/arch/powerpc/ultravisor.rst

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@@ -134,7 +134,7 @@ Hardware 


      * PTCR and partition table entries (partition table is in secure

        memory). An attempt to write to PTCR will cause a Hypervisor

        Emulation Assitance interrupt.

        Emulation Assistance interrupt.



      * LDBAR (LD Base Address Register) and IMC (In-Memory Collection)

        non-architected registers. An attempt to write to them will cause a

Documentation/arch/riscv/vector.rst

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@@ -15,7 +15,7 @@ status for the use of Vector in userspace. The intended usage guideline for 
these interfaces is to give init systems a way to modify the availability of V

for processes running under its domain. Calling these interfaces is not

recommended in libraries routines because libraries should not override policies

configured from the parant process. Also, users must noted that these interfaces

configured from the parent process. Also, users must note that these interfaces

are not portable to non-Linux, nor non-RISC-V environments, so it is discourage

to use in a portable code. To get the availability of V in an ELF program,

please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the

Documentation/arch/x86/mds.rst

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@@ -162,7 +162,7 @@ Mitigation points 
   3. It would take a large number of these precisely-timed NMIs to mount

      an actual attack.  There's presumably not enough bandwidth.

   4. The NMI in question occurs after a VERW, i.e. when user state is

      restored and most interesting data is already scrubbed. Whats left

      restored and most interesting data is already scrubbed. What's left

      is only the data that NMI touches, and that may or may not be of

      any interest.