Commit 455f9075 authored by Daniel J Blueman's avatar Daniel J Blueman Committed by Thomas Gleixner
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x86/tsc: Trust initial offset in architectural TSC-adjust MSRs 



When the BIOS configures the architectural TSC-adjust MSRs on secondary
sockets to correct a constant inter-chassis offset, after Linux brings the
cores online, the TSC sync check later resets the core-local MSR to 0,
triggering HPET fallback and leading to performance loss.

Fix this by unconditionally using the initial adjust values read from the
MSRs. Trusting the initial offsets in this architectural mechanism is a
better approach than special-casing workarounds for specific platforms.

Signed-off-by: default avatarDaniel J Blueman <daniel@quora.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarSteffen Persvold <sp@numascale.com>
Reviewed-by: default avatarJames Cleverdon <james.cleverdon.external@eviden.com>
Reviewed-by: default avatarDimitri Sivanich <sivanich@hpe.com>
Reviewed-by: default avatarPrarit Bhargava <prarit@redhat.com>
Link: https://lore.kernel.org/r/20240419085146.175665-1-daniel@quora.org
parent ed30a4a5

arch/x86/kernel/tsc_sync.c

+2 −4
Original line number Diff line number Diff line
@@ -193,10 +193,8 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) 
	cur->warned = false;



	/*

	 * If a non-zero TSC value for socket 0 may be valid then the default

	 * adjusted value cannot assumed to be zero either.

	 * The default adjust value cannot be assumed to be zero on any socket.

	 */

	if (tsc_async_resets)

	cur->adjusted = bootval;



	/*