Commit 45e51905 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support 



We only support RS480 (AMD based IGP) at the moment not
RS400 (Intel based IGP) ones.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 2735977b

drivers/char/drm/drm_pciids.h

+6 −8
Original line number Diff line number Diff line
@@ -103,20 +103,18 @@ 
	{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \

	{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \

	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \

	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

drivers/char/drm/radeon_cp.c

+70 −99
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
/*

 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.

 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.

 * Copyright 2007 Advanced Micro Devices, Inc.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,7 +41,7 @@ 


static int radeon_do_cleanup_cp(struct drm_device * dev);



static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;

	RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -49,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 
	return ret;

}



static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;

	RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);

	ret = RADEON_READ(RS480_NB_MC_DATA);

	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);

	return ret;

}



static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;

	RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));

	return RADEON_READ(RS690_MC_DATA);

	ret = RADEON_READ(RS690_MC_DATA);

	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);

	return ret;

}



static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)

{

	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)

		return RS690_READ_MCIND(dev_priv, addr);

	else

		return RS480_READ_MCIND(dev_priv, addr);

}



u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)

{



	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)

		return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);

		return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)

		return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)

		return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);

		return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);

	else

		return RADEON_READ(RADEON_MC_FB_LOCATION);

}
@@ -71,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 
static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)

{

	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)

		RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);

		R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)

		RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)

		RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);

		R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);

	else

		RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);

}
@@ -83,11 +104,11 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 
static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)

{

	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)

		RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);

		R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)

		RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);

	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)

		RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);

		R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);

	else

		RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);

}
@@ -106,15 +127,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 
	return RADEON_READ(RADEON_PCIE_DATA);

}



static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)

{

	u32 ret;

	RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f);

	ret = RADEON_READ(RS400_NB_MC_DATA);

	RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);

	return ret;

}



#if RADEON_FIFO_DEBUG

static void radeon_status(drm_radeon_private_t * dev_priv)

{
@@ -255,7 +267,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 
		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {

		DRM_INFO("Loading R300 Microcode\n");

		for (i = 0; i < 256; i++) {

			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -603,115 +615,78 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) 


/* Enable or disable IGP GART on the chip */

static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)

{

	u32 temp, tmp;



	tmp = RADEON_READ(RADEON_AIC_CNTL);

	if (on) {

		DRM_DEBUG("programming igpgart %08X %08lX %08X\n",

			 dev_priv->gart_vm_start,

			 (long)dev_priv->gart_info.bus_addr,

			 dev_priv->gart_size);



		RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN);

		RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |

								    RS400_VA_SIZE_32MB));

		RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN |

							     RS400_TLB_ENABLE |

							     RS400_GTW_LAC_EN |

							     RS400_1LEVEL_GART));

		RADEON_WRITE_IGPGART(RS400_GART_BASE,

				     dev_priv->gart_info.bus_addr);



		temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL);

		RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp);



		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);

		dev_priv->gart_size = 32*1024*1024;

		radeon_write_agp_location(dev_priv,

			     (((dev_priv->gart_vm_start - 1 +

			       dev_priv->gart_size) & 0xffff0000) |

			     (dev_priv->gart_vm_start >> 16)));



		temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);

		RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp);



		RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);

		RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE);

		RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);

		RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0);

       }

}



/* Enable or disable RS690 GART on the chip */

static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)

{

	u32 temp;



	if (on) {

		DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",

		DRM_DEBUG("programming igp gart %08X %08lX %08X\n",

			  dev_priv->gart_vm_start,

			  (long)dev_priv->gart_info.bus_addr,

			  dev_priv->gart_size);



		temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL);

		RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN |

		temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);

		if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)

			IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |

							     RS690_BLOCK_GFX_D3_EN));

		else

			IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);



		RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |

								 RS400_VA_SIZE_32MB));

		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |

							       RS480_VA_SIZE_32MB));



		temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID);

		RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN |

							  RS400_TLB_ENABLE |

							  RS400_GTW_LAC_EN |

							  RS400_1LEVEL_GART));

		temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);

		IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |

							RS480_TLB_ENABLE |

							RS480_GTW_LAC_EN |

							RS480_1LEVEL_GART));



		temp = dev_priv->gart_info.bus_addr & 0xfffff000;

		temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;

		RS690_WRITE_MCIND(RS400_GART_BASE, temp);

		IGP_WRITE_MCIND(RS480_GART_BASE, temp);



		temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL);

		RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) |

							RS400_REQ_TYPE_SNOOP_DIS));

		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);

		IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |

						      RS480_REQ_TYPE_SNOOP_DIS));



		RS690_WRITE_MCIND(RS690_MC_AGP_BASE,

		if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {

			IGP_WRITE_MCIND(RS690_MC_AGP_BASE,

					(unsigned int)dev_priv->gart_vm_start);



		RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);

			IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);

		} else {

			RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);

			RADEON_WRITE(RS480_AGP_BASE_2, 0);

		}



		dev_priv->gart_size = 32*1024*1024;

		temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &

			 0xffff0000) | (dev_priv->gart_vm_start >> 16));



		RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);

		radeon_write_agp_location(dev_priv, temp);



		temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);

		RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |

								 RS400_VA_SIZE_32MB));

		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);

		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |

							       RS480_VA_SIZE_32MB));



		do {

			temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);

			if ((temp & RS690_MC_GART_CLEAR_STATUS) ==

			    RS690_MC_GART_CLEAR_DONE)

			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);

			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)

				break;

			DRM_UDELAY(1);

		} while (1);



		RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL,

				  RS400_GART_CACHE_INVALIDATE);

		IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,

				RS480_GART_CACHE_INVALIDATE);



		do {

			temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);

			if ((temp & RS690_MC_GART_CLEAR_STATUS) ==

			    RS690_MC_GART_CLEAR_DONE)

			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);

			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)

				break;

			DRM_UDELAY(1);

		} while (1);



		RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0);

		IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);

	} else {

		RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0);

		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);

	}

}
@@ -749,12 +724,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 
{

	u32 tmp;



	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {

		radeon_set_rs690gart(dev_priv, on);

		return;

	}



	if (dev_priv->flags & RADEON_IS_IGPGART) {

	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||

	    (dev_priv->flags & RADEON_IS_IGPGART)) {

		radeon_set_igpgart(dev_priv, on);

		return;

	}

drivers/char/drm/radeon_drv.h

+62 −58
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ enum radeon_family { 
	CHIP_RV380,

	CHIP_R420,

	CHIP_RV410,

	CHIP_RS400,

	CHIP_RS480,

	CHIP_RS690,

	CHIP_RV515,

	CHIP_R520,
@@ -459,9 +459,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, 
#define RADEON_PCIE_TX_GART_END_LO	0x16

#define RADEON_PCIE_TX_GART_END_HI	0x17



#define RS400_NB_MC_INDEX               0x168

#	define RS400_NB_MC_IND_WR_EN	(1 << 8)

#define RS400_NB_MC_DATA                0x16c

#define RS480_NB_MC_INDEX               0x168

#	define RS480_NB_MC_IND_WR_EN	(1 << 8)

#define RS480_NB_MC_DATA                0x16c



#define RS690_MC_INDEX                  0x78

#   define RS690_MC_INDEX_MASK          0x1ff
@@ -470,46 +470,42 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, 
#define RS690_MC_DATA                   0x7c



/* MC indirect registers */

#define RS400_MC_MISC_CNTL              0x18

#	define RS400_DISABLE_GTW	(1 << 1)

#define RS480_MC_MISC_CNTL              0x18

#	define RS480_DISABLE_GTW	(1 << 1)

/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */

#	define RS400_GART_INDEX_REG_EN	(1 << 12)

#	define RS480_GART_INDEX_REG_EN	(1 << 12)

#	define RS690_BLOCK_GFX_D3_EN	(1 << 14)

#define RS400_K8_FB_LOCATION            0x1e

#define RS400_GART_FEATURE_ID           0x2b

#	define RS400_HANG_EN	        (1 << 11)

#	define RS400_TLB_ENABLE	        (1 << 18)

#	define RS400_P2P_ENABLE	        (1 << 19)

#	define RS400_GTW_LAC_EN	        (1 << 25)

#	define RS400_2LEVEL_GART	(0 << 30)

#	define RS400_1LEVEL_GART	(1 << 30)

#	define RS400_PDC_EN	        (1 << 31)

#define RS400_GART_BASE                 0x2c

#define RS400_GART_CACHE_CNTRL          0x2e

#	define RS400_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */

/* ??? */

#       define RS690_MC_GART_CLEAR_STATUS   (1 << 1)

#       define RS690_MC_GART_CLEAR_DONE     (0 << 1)

#       define RS690_MC_GART_CLEAR_PENDING  (1 << 1)

#define RS400_AGP_ADDRESS_SPACE_SIZE    0x38

#	define RS400_GART_EN	        (1 << 0)

#	define RS400_VA_SIZE_32MB	(0 << 1)

#	define RS400_VA_SIZE_64MB	(1 << 1)

#	define RS400_VA_SIZE_128MB	(2 << 1)

#	define RS400_VA_SIZE_256MB	(3 << 1)

#	define RS400_VA_SIZE_512MB	(4 << 1)

#	define RS400_VA_SIZE_1GB	(5 << 1)

#	define RS400_VA_SIZE_2GB	(6 << 1)

#define RS400_AGP_MODE_CNTL             0x39

#	define RS400_POST_GART_Q_SIZE	(1 << 18)

#	define RS400_NONGART_SNOOP	(1 << 19)

#	define RS400_AGP_RD_BUF_SIZE	(1 << 20)

#	define RS400_REQ_TYPE_SNOOP_SHIFT 22

#	define RS400_REQ_TYPE_SNOOP_MASK  0x3

#	define RS400_REQ_TYPE_SNOOP_DIS	(1 << 24)

#define RS400_MC_MISC_UMA_CNTL          0x5f

#define RS400_MC_MCLK_CNTL              0x7a

#define RS400_MC_UMA_DUALCH_CNTL        0x86

#define RS480_K8_FB_LOCATION            0x1e

#define RS480_GART_FEATURE_ID           0x2b

#	define RS480_HANG_EN	        (1 << 11)

#	define RS480_TLB_ENABLE	        (1 << 18)

#	define RS480_P2P_ENABLE	        (1 << 19)

#	define RS480_GTW_LAC_EN	        (1 << 25)

#	define RS480_2LEVEL_GART	(0 << 30)

#	define RS480_1LEVEL_GART	(1 << 30)

#	define RS480_PDC_EN	        (1 << 31)

#define RS480_GART_BASE                 0x2c

#define RS480_GART_CACHE_CNTRL          0x2e

#	define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */

#define RS480_AGP_ADDRESS_SPACE_SIZE    0x38

#	define RS480_GART_EN	        (1 << 0)

#	define RS480_VA_SIZE_32MB	(0 << 1)

#	define RS480_VA_SIZE_64MB	(1 << 1)

#	define RS480_VA_SIZE_128MB	(2 << 1)

#	define RS480_VA_SIZE_256MB	(3 << 1)

#	define RS480_VA_SIZE_512MB	(4 << 1)

#	define RS480_VA_SIZE_1GB	(5 << 1)

#	define RS480_VA_SIZE_2GB	(6 << 1)

#define RS480_AGP_MODE_CNTL             0x39

#	define RS480_POST_GART_Q_SIZE	(1 << 18)

#	define RS480_NONGART_SNOOP	(1 << 19)

#	define RS480_AGP_RD_BUF_SIZE	(1 << 20)

#	define RS480_REQ_TYPE_SNOOP_SHIFT 22

#	define RS480_REQ_TYPE_SNOOP_MASK  0x3

#	define RS480_REQ_TYPE_SNOOP_DIS	(1 << 24)

#define RS480_MC_MISC_UMA_CNTL          0x5f

#define RS480_MC_MCLK_CNTL              0x7a

#define RS480_MC_UMA_DUALCH_CNTL        0x86



#define RS690_MC_FB_LOCATION            0x100

#define RS690_MC_AGP_LOCATION           0x101
@@ -529,8 +525,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, 
#define RADEON_MPP_TB_CONFIG		0x01c0

#define RADEON_MEM_CNTL			0x0140

#define RADEON_MEM_SDRAM_MODE_REG	0x0158

#define RADEON_AGP_BASE_2		0x015c

#define RS400_AGP_BASE_2		0x0164

#define RADEON_AGP_BASE_2		0x015c /* r200+ only */

#define RS480_AGP_BASE_2		0x0164

#define RADEON_AGP_BASE			0x0170



#define RADEON_RB3D_COLOROFFSET		0x1c40
@@ -1105,14 +1101,6 @@ do { \ 
	RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));			\

} while (0)



#define RADEON_WRITE_IGPGART(addr, val)				\

do {									\

	RADEON_WRITE(RS400_NB_MC_INDEX,				\

			((addr) & 0x7f) | RS400_NB_MC_IND_WR_EN);	\

	RADEON_WRITE(RS400_NB_MC_DATA, (val));			\

	RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);			\

} while (0)



#define RADEON_WRITE_PCIE(addr, val)					\

do {									\

	RADEON_WRITE8(RADEON_PCIE_INDEX,				\
@@ -1120,13 +1108,21 @@ do { \ 
	RADEON_WRITE(RADEON_PCIE_DATA, (val));			\

} while (0)



#define RADEON_WRITE_MCIND(addr, val)					\

#define R500_WRITE_MCIND(addr, val)					\

do {								\

	RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));	\

	RADEON_WRITE(R520_MC_IND_DATA, (val));			\

	RADEON_WRITE(R520_MC_IND_INDEX, 0);	\

} while (0)



#define RS480_WRITE_MCIND(addr, val)				\

do {									\

	RADEON_WRITE(RS480_NB_MC_INDEX,				\

			((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);	\

	RADEON_WRITE(RS480_NB_MC_DATA, (val));			\

	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);			\

} while (0)



#define RS690_WRITE_MCIND(addr, val)					\

do {								\

	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));	\
@@ -1134,6 +1130,14 @@ do { \ 
	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);	\

} while (0)



#define IGP_WRITE_MCIND(addr, val)				\

do {									\

	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \

		RS690_WRITE_MCIND(addr, val);				\

	else								\

		RS480_WRITE_MCIND(addr, val);				\

} while (0)



#define CP_PACKET0( reg, n )						\

	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))

#define CP_PACKET0_TABLE( reg, n )					\