Commit 45e981b8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/qcom' 

- Drop endpoint redundant masking of global IRQ events (Manivannan
  Sadhasivam)

- Clarify unknown global IRQ message and only log it once to avoid a flood
  (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as maintainer of qcom endpoint driver
  (Manivannan Sadhasivam)

- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
  Sadhasivam)

- Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam)

- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint
  controller (Manivannan Sadhasivam)

- Add global SPI interrupt for PCIe link events to DT binding (Manivannan
  Sadhasivam)

- Add global RC interrupt handler to handle 'Link up' events and
  automatically enumerate hot-added devices (Manivannan Sadhasivam)

- Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR
  MMIO space (Prudhvi Yarlagadda)

- Enable controller resources like PHY only after PERST# is deasserted to
  partially avoid the problem that the endpoint SoC crashes when accessing
  things when Refclk is absent (Manivannan Sadhasivam)

- Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan
  Sadhasivam)

- Cache maximum link speed value in dw_pcie.max_link_speed for use by
  vendor drivers (Manivannan Sadhasivam)

- Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu
  Chinta Venkata)

- Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a
  NULL pointer dereference (Manivannan Sadhasivam)

* pci/controller/qcom:
  PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
  PCI: qcom: Add RX lane margining settings for 16.0 GT/s
  PCI: qcom: Add equalization settings for 16.0 GT/s
  PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
  PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
  PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
  PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
  PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
  dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
  PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
  PCI: endpoint: Assign PCI domain number for endpoint controllers
  dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
  dt-bindings: PCI: pci-ep: Update Maintainers
  PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
  PCI: qcom-ep: Drop the redundant masking of global IRQ events
parents 1bcf2331 0cca961a

Documentation/devicetree/bindings/pci/pci-ep.yaml

+13 −1
Original line number Diff line number Diff line
@@ -10,7 +10,8 @@ description: | 
  Common properties for PCI Endpoint Controller Nodes.



maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>

  - Kishon Vijay Abraham I <kishon@kernel.org>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



properties:

  $nodename:
@@ -41,6 +42,17 @@ properties: 
    default: 1

    maximum: 16



  linux,pci-domain:

    description:

      If present this property assigns a fixed PCI domain number to a PCI

      Endpoint Controller, otherwise an unstable (across boots) unique number

      will be assigned. It is required to either not set this property at all

      or set it for all PCI endpoint controllers in the system, otherwise

      potentially conflicting domain numbers may be assigned to endpoint

      controllers. The domain number for each endpoint controller in the system

      must be unique.

    $ref: /schemas/types.yaml#/definitions/uint32



required:

  - compatible

Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml

+2 −2
Original line number Diff line number Diff line
@@ -21,11 +21,11 @@ properties: 


  interrupts:

    minItems: 1

    maxItems: 8

    maxItems: 9



  interrupt-names:

    minItems: 1

    maxItems: 8

    maxItems: 9



  iommu-map:

    minItems: 1

Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml

+1 −0
Original line number Diff line number Diff line
@@ -280,4 +280,5 @@ examples: 
        phy-names = "pciephy";

        max-link-speed = <3>;

        num-lanes = <2>;

        linux,pci-domain = <0>;

    };

Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml

+6 −4
Original line number Diff line number Diff line
@@ -55,8 +55,8 @@ properties: 
      - const: aggre1 # Aggre NoC PCIe1 AXI clock



  interrupts:

    minItems: 8

    maxItems: 8

    minItems: 9

    maxItems: 9



  interrupt-names:

    items:
@@ -68,6 +68,7 @@ properties: 
      - const: msi5

      - const: msi6

      - const: msi7

      - const: global



  operating-points-v2: true

  opp-table:
@@ -149,9 +150,10 @@ examples: 
                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi0", "msi1", "msi2", "msi3",

                              "msi4", "msi5", "msi6", "msi7";

                              "msi4", "msi5", "msi6", "msi7", "global";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

MAINTAINERS

+3 −1
Original line number Diff line number Diff line
@@ -2728,7 +2728,7 @@ F: drivers/iommu/msm* 
F:	drivers/mfd/ssbi.c

F:	drivers/mmc/host/mmci_qcom*

F:	drivers/mmc/host/sdhci-msm.c

F:	drivers/pci/controller/dwc/pcie-qcom.c

F:	drivers/pci/controller/dwc/pcie-qcom*

F:	drivers/phy/qualcomm/

F:	drivers/power/*/msm*

F:	drivers/reset/reset-qcom-*
@@ -17754,6 +17754,7 @@ M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 
L:	linux-pci@vger.kernel.org

L:	linux-arm-msm@vger.kernel.org

S:	Maintained

F:	drivers/pci/controller/dwc/pcie-qcom-common.c

F:	drivers/pci/controller/dwc/pcie-qcom.c









PCIE DRIVER FOR ROCKCHIP








@@ -17790,6 +17791,7 @@ L:	linux-pci@vger.kernel.org







L:	linux-arm-msm@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml









F:	drivers/pci/controller/dwc/pcie-qcom-common.c









F:	drivers/pci/controller/dwc/pcie-qcom-ep.c

















PCMCIA SUBSYSTEM