Unverified Commit 4630d6da authored by Palmer Dabbelt's avatar Palmer Dabbelt
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Merge patch "riscv: errata: improve T-Head CMO" 

This fixes an encoding issue with T-Head's dcache.cva and fixes the
comment about the T-Head encodings.  The first of these was a fix and
got picked up earlier, I'm merging the second on top of it as they touch
the same comment.

* b4-shazam-merge:
  riscv: errata: prefix T-Head mnemonics with th.
  riscv: errata: fix T-Head dcache.cva encoding

Link: https://lore.kernel.org/r/20230827090813.1353-1-jszhang@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents b8c2f661 27fb2719

arch/riscv/include/asm/errata_list.h

+9 −9
Original line number Diff line number Diff line
@@ -95,30 +95,30 @@ asm volatile(ALTERNATIVE( \ 
#endif



/*

 * dcache.ipa rs1 (invalidate, physical address)

 * th.dcache.ipa rs1 (invalidate, physical address)

 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

 *   0000001    01010      rs1       000      00000  0001011

 * dache.iva rs1 (invalida, virtual address)

 * th.dache.iva rs1 (invalida, virtual address)

 *   0000001    00110      rs1       000      00000  0001011

 *

 * dcache.cpa rs1 (clean, physical address)

 * th.dcache.cpa rs1 (clean, physical address)

 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

 *   0000001    01001      rs1       000      00000  0001011

 * dcache.cva rs1 (clean, virtual address)

 *   0000001    00100      rs1       000      00000  0001011

 * th.dcache.cva rs1 (clean, virtual address)

 *   0000001    00101      rs1       000      00000  0001011

 *

 * dcache.cipa rs1 (clean then invalidate, physical address)

 * th.dcache.cipa rs1 (clean then invalidate, physical address)

 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

 *   0000001    01011      rs1       000      00000  0001011

 * dcache.civa rs1 (... virtual address)

 * th.dcache.civa rs1 (... virtual address)

 *   0000001    00111      rs1       000      00000  0001011

 *

 * sync.s (make sure all cache operations finished)

 * th.sync.s (make sure all cache operations finished)

 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |

 *   0000000    11001     00000      000      00000  0001011

 */

#define THEAD_inval_A0	".long 0x0265000b"

#define THEAD_clean_A0	".long 0x0245000b"

#define THEAD_clean_A0	".long 0x0255000b"

#define THEAD_flush_A0	".long 0x0275000b"

#define THEAD_SYNC_S	".long 0x0190000b"