Commit 4632e320 authored by Shekhar Chauhan's avatar Shekhar Chauhan Committed by Matt Roper
Browse files

drm/i915: Add Wa_14015150844 



Disables Atomic-chaining of Typed Writes.

BSpec: 54040
Signed-off-by: default avatarShekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901045700.2553994-1-shekhar.chauhan@intel.com
parent fb4e4c5e

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -1218,6 +1218,8 @@ 


#define XEHP_HDC_CHICKEN0			MCR_REG(0xe5f0)

#define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)

#define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)



#define ICL_HDC_MODE				MCR_REG(0xe5f4)



#define EU_PERF_CNTL2				PERF_REG(0xe658)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+8 −0
Original line number Diff line number Diff line
@@ -2326,6 +2326,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
				  LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);

	}



	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

	    IS_DG2(i915)) {

		/* Wa_14015150844 */

		wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,

			   _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),

			   0, true);

	}



	if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {

		/* Wa_22014600077:dg2 */

		wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,