Commit 46a301e1 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: drop unnecessary Navi1x specific APIs 



As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5a52694c

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+1 −247
Original line number Diff line number Diff line
@@ -1376,59 +1376,6 @@ static int navi10_display_config_changed(struct smu_context *smu) 
	return ret;

}



static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)

{

	int ret = 0, i = 0;

	uint32_t min_freq, max_freq, force_freq;

	enum smu_clk_type clk_type;



	enum smu_clk_type clks[] = {

		SMU_GFXCLK,

		SMU_MCLK,

		SMU_SOCCLK,

	};



	for (i = 0; i < ARRAY_SIZE(clks); i++) {

		clk_type = clks[i];

		ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;



		force_freq = highest ? max_freq : min_freq;

		ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);

		if (ret)

			return ret;

	}



	return ret;

}



static int navi10_unforce_dpm_levels(struct smu_context *smu)

{

	int ret = 0, i = 0;

	uint32_t min_freq, max_freq;

	enum smu_clk_type clk_type;



	enum smu_clk_type clks[] = {

		SMU_GFXCLK,

		SMU_MCLK,

		SMU_SOCCLK,

	};



	for (i = 0; i < ARRAY_SIZE(clks); i++) {

		clk_type = clks[i];

		ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;



		ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

		if (ret)

			return ret;

	}



	return ret;

}



static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)

{

	if (!value)
@@ -1681,47 +1628,6 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u 
	return ret;

}



static int navi10_get_profiling_clk_mask(struct smu_context *smu,

					 enum amd_dpm_forced_level level,

					 uint32_t *sclk_mask,

					 uint32_t *mclk_mask,

					 uint32_t *soc_mask)

{

	int ret = 0;

	uint32_t level_count = 0;



	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (sclk_mask)

			*sclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {

		if (mclk_mask)

			*mclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {

		if(sclk_mask) {

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK, &level_count);

			if (ret)

				return ret;

			*sclk_mask = level_count - 1;

		}



		if(mclk_mask) {

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK, &level_count);

			if (ret)

				return ret;

			*mclk_mask = level_count - 1;

		}



		if(soc_mask) {

			ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);

			if (ret)

				return ret;

			*soc_mask = level_count - 1;

		}

	}



	return ret;

}



static int navi10_notify_smc_display_config(struct smu_context *smu)

{

	struct smu_clocks min_clocks = {0};
@@ -1954,155 +1860,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_ 
	return 0;

}



static int navi10_set_performance_level(struct smu_context *smu,

					enum amd_dpm_forced_level level);



static int navi10_set_standard_performance_level(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint32_t sclk_freq = 0, uclk_freq = 0;



	switch (adev->asic_type) {

	case CHIP_NAVI10:

		sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;

		uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;

		break;

	case CHIP_NAVI14:

		sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;

		uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;

		break;

	default:

		/* by default, this is same as auto performance level */

		return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);

	}



	ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);

	if (ret)

		return ret;

	ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);

	if (ret)

		return ret;



	return ret;

}



static int navi10_set_peak_performance_level(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint32_t sclk_freq = 0, uclk_freq = 0;



	switch (adev->asic_type) {

	case CHIP_NAVI10:

		switch (adev->pdev->revision) {

		case 0xf0: /* XTX */

		case 0xc0:

			sclk_freq = NAVI10_PEAK_SCLK_XTX;

			break;

		case 0xf1: /* XT */

		case 0xc1:

			sclk_freq = NAVI10_PEAK_SCLK_XT;

			break;

		default: /* XL */

			sclk_freq = NAVI10_PEAK_SCLK_XL;

			break;

		}

		break;

	case CHIP_NAVI14:

		switch (adev->pdev->revision) {

		case 0xc7: /* XT */

		case 0xf4:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;

			break;

		case 0xc1: /* XTM */

		case 0xf2:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;

			break;

		case 0xc3: /* XLM */

		case 0xf3:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;

			break;

		case 0xc5: /* XTX */

		case 0xf6:

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;

			break;

		default: /* XL */

			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;

			break;

		}

		break;

	case CHIP_NAVI12:

		sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;

		break;

	default:

		ret = smu_v11_0_get_dpm_level_range(smu,

						    SMU_SCLK,

						    NULL,

						    &sclk_freq);

		if (ret)

			return ret;

	}



	ret = smu_v11_0_get_dpm_level_range(smu,

					    SMU_UCLK,

					    NULL,

					    &uclk_freq);

	if (ret)

		return ret;



	ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);

	if (ret)

		return ret;

	ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);

	if (ret)

		return ret;



	return ret;

}



static int navi10_set_performance_level(struct smu_context *smu,

					enum amd_dpm_forced_level level)

{

	int ret = 0;

	uint32_t sclk_mask, mclk_mask, soc_mask;



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

		ret = smu_force_dpm_limit_value(smu, true);

		break;

	case AMD_DPM_FORCED_LEVEL_LOW:

		ret = smu_force_dpm_limit_value(smu, false);

		break;

	case AMD_DPM_FORCED_LEVEL_AUTO:

		ret = smu_unforce_dpm_levels(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:

		ret = navi10_set_standard_performance_level(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

		ret = smu_get_profiling_clk_mask(smu, level,

						 &sclk_mask,

						 &mclk_mask,

						 &soc_mask);

		if (ret)

			return ret;

		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);

		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);

		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

		ret = navi10_set_peak_performance_level(smu);

		break;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:

	default:

		break;

	}

	return ret;

}



static int navi10_get_thermal_temperature_range(struct smu_context *smu,

						struct smu_temperature_range *range)

{
@@ -2622,18 +2379,15 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.pre_display_config_changed = navi10_pre_display_config_changed,

	.display_config_changed = navi10_display_config_changed,

	.notify_smc_display_config = navi10_notify_smc_display_config,

	.force_dpm_limit_value = navi10_force_dpm_limit_value,

	.unforce_dpm_levels = navi10_unforce_dpm_levels,

	.is_dpm_running = navi10_is_dpm_running,

	.get_fan_speed_percent = navi10_get_fan_speed_percent,

	.get_fan_speed_rpm = navi10_get_fan_speed_rpm,

	.get_power_profile_mode = navi10_get_power_profile_mode,

	.set_power_profile_mode = navi10_set_power_profile_mode,

	.get_profiling_clk_mask = navi10_get_profiling_clk_mask,

	.set_watermarks_table = navi10_set_watermarks_table,

	.read_sensor = navi10_read_sensor,

	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,

	.set_performance_level = navi10_set_performance_level,

	.set_performance_level = smu_v11_0_set_performance_level,

	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,

	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,

	.get_power_limit = navi10_get_power_limit,