Commit 46c1282e authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: add gfx11 emit shadow callback 



Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.

v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
    Only set IB_VMID when a valid shadow buffer is present
    (Alex)
v5: Pass parameters rather than job to new ring callback (Alex)

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac928705

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+25 −0
Original line number Diff line number Diff line
@@ -5608,6 +5608,29 @@ static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 
	amdgpu_ring_write(ring, 0);

}



static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,

					   u64 shadow_va, u64 csa_va,

					   u64 gds_va, bool init_shadow,

					   int vmid)

{

	struct amdgpu_device *adev = ring->adev;



	if (!adev->gfx.cp_gfx_shadow)

		return;



	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));

	amdgpu_ring_write(ring, lower_32_bits(shadow_va));

	amdgpu_ring_write(ring, upper_32_bits(shadow_va));

	amdgpu_ring_write(ring, lower_32_bits(gds_va));

	amdgpu_ring_write(ring, upper_32_bits(gds_va));

	amdgpu_ring_write(ring, lower_32_bits(csa_va));

	amdgpu_ring_write(ring, upper_32_bits(csa_va));

	amdgpu_ring_write(ring, shadow_va ?

			  PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);

	amdgpu_ring_write(ring, init_shadow ?

			  PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);

}



static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)

{

	unsigned ret;
@@ -6228,6 +6251,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 
	.set_wptr = gfx_v11_0_ring_set_wptr_gfx,

	.emit_frame_size = /* totally 242 maximum if 16 IBs */

		5 + /* COND_EXEC */

		9 + /* SET_Q_PREEMPTION_MODE */

		7 + /* PIPELINE_SYNC */

		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +

		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
@@ -6254,6 +6278,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 
	.insert_nop = amdgpu_ring_insert_nop,

	.pad_ib = amdgpu_ring_generic_pad_ib,

	.emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,

	.emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,

	.init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,

	.patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,

	.preempt_ib = gfx_v11_0_ring_preempt_ib,

drivers/gpu/drm/amd/amdgpu/nvd.h

+4 −1
Original line number Diff line number Diff line
@@ -462,6 +462,9 @@ 
#              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)

#define	PACKET3_RUN_LIST				0xA5

#define	PACKET3_MAP_PROCESS_VM				0xA6



/* GFX11 */

#define	PACKET3_SET_Q_PREEMPTION_MODE			0xF0

#              define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x)  ((x) << 0)

#              define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM    (1 << 0)



#endif