Commit 46da08a2 authored by Zide Chen's avatar Zide Chen Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add missing PMON units for Panther Lake 



Besides CBOX, Panther Lake includes several legacy uncore PMON units
not enumerated via discovery tables, including cNCU, SANTA, and
ia_core_bridge.

The cNCU PMON is similar to Meteor Lake but has two boxes with two
counters each. SANTA and IA Core Bridge PMON units follow the legacy
model used on Lunar Lake, Meteor Lake, and others.

Panther Lake implements the Global Control Register; the freeze_all bit
must be cleared before programming counters.

Signed-off-by: default avatarZide Chen <zide.chen@intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251231224233.113839-13-zide.chen@intel.com
parent 2246c244

arch/x86/events/intel/uncore.c

+1 −0
Original line number Diff line number Diff line
@@ -1814,6 +1814,7 @@ static const struct uncore_plat_init ptl_uncore_init __initconst = { 
	.cpu_init = ptl_uncore_cpu_init,

	.mmio_init = ptl_uncore_mmio_init,

	.domain[0].discovery_base = UNCORE_DISCOVERY_MSR,

	.domain[0].global_init = uncore_mmio_global_init,

};



static const struct uncore_plat_init icx_uncore_init __initconst = {

arch/x86/events/intel/uncore_snb.c

+45 −0
Original line number Diff line number Diff line
@@ -245,6 +245,17 @@ 
#define MTL_UNC_HBO_CTR				0x2048

#define MTL_UNC_HBO_CTRL			0x2042



/* PTL Low Power Bridge register */

#define PTL_UNC_IA_CORE_BRIDGE_PER_CTR0		0x2028

#define PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0	0x2022



/* PTL Santa register */

#define PTL_UNC_SANTA_CTR0			0x2418

#define PTL_UNC_SANTA_CTRL0			0x2412



/* PTL cNCU register */

#define PTL_UNC_CNCU_MSR_OFFSET			0x140



DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");

DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");

DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
@@ -1921,8 +1932,36 @@ void ptl_uncore_mmio_init(void) 
						 ptl_uncores);

}



static struct intel_uncore_type ptl_uncore_ia_core_bridge = {

	.name		= "ia_core_bridge",

	.num_counters   = 2,

	.num_boxes	= 1,

	.perf_ctr_bits	= 48,

	.perf_ctr	= PTL_UNC_IA_CORE_BRIDGE_PER_CTR0,

	.event_ctl	= PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0,

	.event_mask	= ADL_UNC_RAW_EVENT_MASK,

	.ops		= &icl_uncore_msr_ops,

	.format_group	= &adl_uncore_format_group,

};



static struct intel_uncore_type ptl_uncore_santa = {

	.name		= "santa",

	.num_counters   = 2,

	.num_boxes	= 2,

	.perf_ctr_bits	= 48,

	.perf_ctr	= PTL_UNC_SANTA_CTR0,

	.event_ctl	= PTL_UNC_SANTA_CTRL0,

	.event_mask	= ADL_UNC_RAW_EVENT_MASK,

	.msr_offset	= SNB_UNC_CBO_MSR_OFFSET,

	.ops		= &icl_uncore_msr_ops,

	.format_group	= &adl_uncore_format_group,

};



static struct intel_uncore_type *ptl_msr_uncores[] = {

	&mtl_uncore_cbox,

	&ptl_uncore_ia_core_bridge,

	&ptl_uncore_santa,

	&mtl_uncore_cncu,

	NULL

};
@@ -1930,6 +1969,12 @@ void ptl_uncore_cpu_init(void) 
{

	mtl_uncore_cbox.num_boxes = 6;

	mtl_uncore_cbox.ops = &lnl_uncore_msr_ops;



	mtl_uncore_cncu.num_counters = 2;

	mtl_uncore_cncu.num_boxes = 2;

	mtl_uncore_cncu.msr_offset = PTL_UNC_CNCU_MSR_OFFSET;

	mtl_uncore_cncu.single_fixed = 0;



	uncore_msr_uncores = ptl_msr_uncores;

}