Commit 46dcf855 authored by Ravi Bangoria's avatar Ravi Bangoria Committed by Peter Zijlstra
Browse files

perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCnt 



IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with
the desired sample period. IBS hw generates sample when CurCnt reaches
to MaxCnt. The size of these counter used to be 20 bits but later they
were extended to 27 bits. The 7 bit extension is indicated by CPUID
Fn8000_001B_EAX[6 / OpCntExt].

perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt.
But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even
when OpCntExt CPUID bit is set. Fix this.

IBS driver uses cnt_mask[CurCnt] bits only while disabling an event.
Fortunately, CurCnt bits are not read from MSR while re-enabling the
event, instead MaxCnt is programmed with desired period and CurCnt is
set to 0. Hence, we did not see any issues so far.

Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com
parent 598bdf4f

arch/x86/events/amd/ibs.c

+2 −1
Original line number Diff line number Diff line
@@ -1245,7 +1245,8 @@ static __init int perf_ibs_op_init(void) 
	if (ibs_caps & IBS_CAPS_OPCNTEXT) {

		perf_ibs_op.max_period  |= IBS_OP_MAX_CNT_EXT_MASK;

		perf_ibs_op.config_mask	|= IBS_OP_MAX_CNT_EXT_MASK;

		perf_ibs_op.cnt_mask    |= IBS_OP_MAX_CNT_EXT_MASK;

		perf_ibs_op.cnt_mask    |= (IBS_OP_MAX_CNT_EXT_MASK |

					    IBS_OP_CUR_CNT_EXT_MASK);

	}



	if (ibs_caps & IBS_CAPS_ZEN4)

arch/x86/include/asm/perf_event.h

+1 −0
Original line number Diff line number Diff line
@@ -514,6 +514,7 @@ struct pebs_xmm { 
 */

#define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)

#define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)

#define IBS_OP_CUR_CNT_EXT_MASK	(0x7FULL<<52)

#define IBS_OP_CNT_CTL		(1ULL<<19)

#define IBS_OP_VAL		(1ULL<<18)

#define IBS_OP_ENABLE		(1ULL<<17)