Commit 46e15197 authored by Sonny Jiang's avatar Sonny Jiang Committed by Alex Deucher
Browse files

drm/amdgpu: VCN v5_0_1 to prevent FW checking RB during DPG pause 



Add a protection to ensure programming are all complete prior VCPU
starting. This is a WA for an unintended VCPU running.

Signed-off-by: default avatarSonny Jiang <sonny.jiang@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c29521b5)
Cc: stable@vger.kernel.org
parent caade9d6

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

+5 −1
Original line number Diff line number Diff line
@@ -669,6 +669,9 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 
	if (indirect)

		amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);



	/* resetting ring, fw should not check RB ring */

	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;



	/* Pause dpg */

	vcn_v5_0_1_pause_dpg_mode(vinst, &state);
@@ -681,7 +684,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 
	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);

	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);

	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;



	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);

	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
@@ -692,6 +695,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 
	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;

	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);

	/* resetting done, fw can check RB ring */

	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);



	WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,