Commit 46f74a3f authored by Heiko Schocher's avatar Heiko Schocher Committed by Paolo Abeni
Browse files

net: phy: dp83869: fix setting CLK_O_SEL field. 



Table 7-121 in datasheet says we have to set register 0xc6
to value 0x10 before CLK_O_SEL can be modified. No more infos
about this field found in datasheet. With this fix, setting
of CLK_O_SEL field in IO_MUX_CFG register worked through dts
property "ti,clk-output-sel" on a DP83869HMRGZR.

Signed-off-by: default avatarHeiko Schocher <hs@nabladev.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Fixes: 01db923e ("net: phy: dp83869: Add TI dp83869 phy")
Link: https://patch.msgid.link/20260425031339.3318-1-hs@nabladev.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 4ca07b92

drivers/net/phy/dp83869.c

+12 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define DP83869_RGMIICTL	0x0032

#define DP83869_STRAP_STS1	0x006e

#define DP83869_RGMIIDCTL	0x0086

#define DP83869_ANA_PLL_PROG_PI	0x00c6

#define DP83869_RXFCFG		0x0134

#define DP83869_RXFPMD1		0x0136

#define DP83869_RXFPMD2		0x0137
@@ -826,12 +827,22 @@ static int dp83869_config_init(struct phy_device *phydev) 
		dp83869_config_port_mirroring(phydev);



	/* Clock output selection if muxing property is set */

	if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)

	if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) {

		/*

		 * Table 7-121 in datasheet says we have to set register 0xc6

		 * to value 0x10 before CLK_O_SEL can be modified.

		 */

		ret = phy_write_mmd(phydev, DP83869_DEVADDR,

				    DP83869_ANA_PLL_PROG_PI, 0x10);

		if (ret)

			return ret;



		ret = phy_modify_mmd(phydev,

				     DP83869_DEVADDR, DP83869_IO_MUX_CFG,

				     DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,

				     dp83869->clk_output_sel <<

				     DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);

	}



	if (phy_interface_is_rgmii(phydev)) {

		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,