Commit 47687aa4 authored by Jeremy Linton's avatar Jeremy Linton Committed by Will Deacon
Browse files

arm64: probes: Break ret out from bl/blr 



Prepare for GCS by breaking RET out into its own function, where
it makes more sense to encapsulate the new behavior independent
from the branch instructions.

Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 8f5ae30d

arch/arm64/kernel/probes/decode-insn.c

+4 −3
Original line number Diff line number Diff line
@@ -108,9 +108,10 @@ arm_probe_decode_insn(u32 insn, struct arch_probe_insn *api) 
	    aarch64_insn_is_bl(insn)) {

		api->handler = simulate_b_bl;

	} else if (aarch64_insn_is_br(insn) ||

	    aarch64_insn_is_blr(insn) ||

	    aarch64_insn_is_ret(insn)) {

		api->handler = simulate_br_blr_ret;

		aarch64_insn_is_blr(insn)) {

		api->handler = simulate_br_blr;

	} else if (aarch64_insn_is_ret(insn)) {

		api->handler = simulate_ret;

	} else {

		/*

		 * Instruction cannot be stepped out-of-line and we don't

arch/arm64/kernel/probes/simulate-insn.c

+9 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs) 
}



void __kprobes

simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs)

simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs)

{

	int xn = (opcode >> 5) & 0x1f;
@@ -138,6 +138,14 @@ simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs) 
		set_x_reg(regs, 30, addr + 4);

}



void __kprobes

simulate_ret(u32 opcode, long addr, struct pt_regs *regs)

{

	int xn = (opcode >> 5) & 0x1f;



	instruction_pointer_set(regs, get_x_reg(regs, xn));

}



void __kprobes

simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs)

{

arch/arm64/kernel/probes/simulate-insn.h

+2 −1
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ 
void simulate_adr_adrp(u32 opcode, long addr, struct pt_regs *regs);

void simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs);

void simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs);

void simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs);

void simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs);

void simulate_ret(u32 opcode, long addr, struct pt_regs *regs);

void simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs);

void simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs);

void simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs);