Commit 479e25d8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2025-12-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v6.19:

GPU:
- Fix crash on a7xx GPUs not supporting IFPC
- Fix perfcntr use with IFPC
- Concurrent binning fix

DPU:
- Fixed DSC and SSPP fetching issues
- Switched to scnprint instead of snprintf
- Added missing NULL checks in pingpong code

Also documentation fixes.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV01jcLLChsFtmqc4VDNoQ2ic2q+d86n3wdoSUdmW6xaSdQ@mail.gmail.com
parents 9448598b 66691e27

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+12 −1
Original line number Diff line number Diff line
@@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { 
	REG_A6XX_UCHE_MODE_CNTL,

	REG_A6XX_RB_NC_MODE_CNTL,

	REG_A6XX_RB_CMP_DBG_ECO_CNTL,

	REG_A7XX_GRAS_NC_MODE_CNTL,

	REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,

	REG_A6XX_UCHE_GBIF_GX_CONFIG,

	REG_A6XX_UCHE_CLIENT_PF,
@@ -1392,6 +1391,7 @@ static const u32 a750_ifpc_reglist_regs[] = { 
	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),

	REG_A6XX_RBBM_PERFCTR_CNTL,

	REG_A6XX_TPL1_NC_MODE_CNTL,

	REG_A6XX_SP_NC_MODE_CNTL,

	REG_A6XX_CP_DBG_ECO_CNTL,
@@ -1448,6 +1448,12 @@ static const u32 a750_ifpc_reglist_regs[] = { 


DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);



static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = {

	{ REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },

};



DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist);



static const struct adreno_info a7xx_gpus[] = {

	{

		.chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1491,6 +1497,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a730_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020000,

		},
@@ -1513,6 +1520,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a740_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7020100,

			.gmu_cgc_mode = 0x00020202,
@@ -1547,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a740_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,

			.ifpc_reglist = &a750_ifpc_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7050001,
@@ -1589,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,

			.ifpc_reglist = &a750_ifpc_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7090100,
@@ -1623,6 +1633,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a740_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x70f0000,

			.gmu_cgc_mode = 0x00020222,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+40 −12
Original line number Diff line number Diff line
@@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
		  min_acc_len_64b << 3 |

		  hbb_lo << 1 | ubwc_mode);



	if (adreno_is_a7xx(adreno_gpu))

	if (adreno_is_a7xx(adreno_gpu)) {

		for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {

			gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,

				  A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));

			gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,

				  FIELD_PREP(GENMASK(8, 5), hbb_lo));

		}

		gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,

			  A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));

	}



	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,

		  min_acc_len_64b << 23 | hbb_lo << 21);
@@ -865,14 +872,17 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

	const struct adreno_reglist_list *reglist;

	const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;

	void *ptr = a6xx_gpu->pwrup_reglist_ptr;

	struct cpu_gpu_lock *lock = ptr;

	u32 *dest = (u32 *)&lock->regs[0];

	u32 dyn_pwrup_reglist_count = 0;

	int i;



	lock->gpu_req = lock->cpu_req = lock->turn = 0;



	reglist = adreno_gpu->info->a6xx->ifpc_reglist;

	if (reglist) {

		lock->ifpc_list_len = reglist->count;



		/*
@@ -883,6 +893,7 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 
			*dest++ = reglist->regs[i];

			*dest++ = gpu_read(gpu, reglist->regs[i]);

		}

	}



	reglist = adreno_gpu->info->a6xx->pwrup_reglist;

	lock->preemption_list_len = reglist->count;
@@ -907,7 +918,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 
	 * (<aperture, shifted 12 bits> <address> <data>), and the length is

	 * stored as number for triplets in dynamic_list_len.

	 */

	lock->dynamic_list_len = 0;

	dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist;

	if (dyn_pwrup_reglist) {

		for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {

			gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,

				  A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));

			for (i = 0; i < dyn_pwrup_reglist->count; i++) {

				if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == 0)

					continue;

				*dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);

				*dest++ = dyn_pwrup_reglist->regs[i].offset;

				*dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset);

				dyn_pwrup_reglist_count++;

			}

		}

		gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,

			  A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));

	}

	lock->dynamic_list_len = dyn_pwrup_reglist_count;

}



static int a7xx_preempt_start(struct msm_gpu *gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ struct a6xx_info { 
	const struct adreno_reglist *hwcg;

	const struct adreno_protect *protect;

	const struct adreno_reglist_list *pwrup_reglist;

	const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;

	const struct adreno_reglist_list *ifpc_reglist;

	const struct adreno_reglist *gbif_cx;

	const struct adreno_reglist_pipe *nonctxt_reglist;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

+2 −2
Original line number Diff line number Diff line
@@ -454,11 +454,11 @@ void a6xx_preempt_init(struct msm_gpu *gpu) 
			gpu->vm, &a6xx_gpu->preempt_postamble_bo,

			&a6xx_gpu->preempt_postamble_iova);



	preempt_prepare_postamble(a6xx_gpu);



	if (IS_ERR(a6xx_gpu->preempt_postamble_ptr))

		goto fail;



	preempt_prepare_postamble(a6xx_gpu);



	timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0);



	return;

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+13 −0
Original line number Diff line number Diff line
@@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \ 
	.count = ARRAY_SIZE(name ## _regs),		\

};



struct adreno_reglist_pipe_list {

	/** @reg: List of register **/

	const struct adreno_reglist_pipe *regs;

	/** @count: Number of registers in the list **/

	u32 count;

};



#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name)	\

static const struct adreno_reglist_pipe_list name = {		\

	.regs = name ## _regs,				\

	.count = ARRAY_SIZE(name ## _regs),		\

};



struct adreno_gpu {

	struct msm_gpu base;

	const struct adreno_info *info;