Commit 47ae1f93 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add support for GC IP version 11.5.4 



This initializes GC IP version 11.5.4.

v2: squash in RLC offset fix

Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bc35ae1a

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+6 −0
Original line number Diff line number Diff line
@@ -1988,6 +1988,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -2047,6 +2048,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -2358,6 +2360,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -2559,6 +2562,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);

		adev->enable_mes = true;

		adev->enable_mes_kiq = true;
@@ -2961,6 +2965,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		adev->family = AMDGPU_FAMILY_GC_11_5_0;

		break;

	case IP_VERSION(12, 0, 0):
@@ -2988,6 +2993,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		adev->flags |= AMD_IS_APU;

		break;

	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −0
Original line number Diff line number Diff line
@@ -949,6 +949,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		/* Don't enable it by default yet.

		 */

		if (amdgpu_tmz < 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+11 −1
Original line number Diff line number Diff line
@@ -120,6 +120,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 
MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_4_pfp.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_4_me.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_4_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_4_rlc.bin");



static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
@@ -1113,6 +1117,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1595,6 +1600,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 2;
@@ -3052,7 +3058,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 
		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||

		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||

		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) ||

		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3))

		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) ||

		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4))

			bootload_status = RREG32_SOC15(GC, 0,

					regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);

		else
@@ -5640,6 +5647,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 
		case IP_VERSION(11, 5, 1):

		case IP_VERSION(11, 5, 2):

		case IP_VERSION(11, 5, 3):

	        case IP_VERSION(11, 5, 4):

			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);

			break;

		default:
@@ -5678,6 +5686,7 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		if (!enable)

			amdgpu_gfx_off_ctrl(adev, false);
@@ -5712,6 +5721,7 @@ static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

	        gfx_v11_0_update_gfx_clock_gating(adev,

	                        state ==  AMD_CG_STATE_GATE);

	        break;

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+2 −0
Original line number Diff line number Diff line
@@ -602,6 +602,7 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;

		break;

	default:
@@ -778,6 +779,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

	case IP_VERSION(11, 5, 4):

		set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);

		set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);

		/*

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin"); 
MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin");



static int imu_v11_0_init_microcode(struct amdgpu_device *adev)

{