Unverified Commit 47b9533c authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "tools: Add barrier implementations for riscv" 

Charlie Jenkins <charlie@rivosinc.com> says:

Add support for riscv specific barrier implementations to the tools
tree, so that fence instructions can be emitted for synchronization.

* b4-shazam-merge:
  tools: Optimize ring buffer for riscv
  tools: Add riscv barrier implementation

Link: https://lore.kernel.org/r/20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents ad380f6a aa5736dc

tools/arch/riscv/include/asm/barrier.h

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+39 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copied from the kernel sources to tools/arch/riscv:

 *

 * Copyright (C) 2012 ARM Ltd.

 * Copyright (C) 2013 Regents of the University of California

 * Copyright (C) 2017 SiFive

 */



#ifndef _TOOLS_LINUX_ASM_RISCV_BARRIER_H

#define _TOOLS_LINUX_ASM_RISCV_BARRIER_H



#include <asm/fence.h>

#include <linux/compiler.h>



/* These barriers need to enforce ordering on both devices and memory. */

#define mb()		RISCV_FENCE(iorw, iorw)

#define rmb()		RISCV_FENCE(ir, ir)

#define wmb()		RISCV_FENCE(ow, ow)



/* These barriers do not need to enforce ordering on devices, just memory. */

#define smp_mb()	RISCV_FENCE(rw, rw)

#define smp_rmb()	RISCV_FENCE(r, r)

#define smp_wmb()	RISCV_FENCE(w, w)



#define smp_store_release(p, v)						\

do {									\

	RISCV_FENCE(rw, w);						\

	WRITE_ONCE(*p, v);						\

} while (0)



#define smp_load_acquire(p)						\

({									\

	typeof(*p) ___p1 = READ_ONCE(*p);				\

	RISCV_FENCE(r, rw);						\

	___p1;								\

})



#endif /* _TOOLS_LINUX_ASM_RISCV_BARRIER_H */

tools/arch/riscv/include/asm/fence.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copied from the kernel sources to tools/arch/riscv:

 */



#ifndef _ASM_RISCV_FENCE_H

#define _ASM_RISCV_FENCE_H



#define RISCV_FENCE_ASM(p, s)		"\tfence " #p "," #s "\n"

#define RISCV_FENCE(p, s) \

	({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); })



#endif	/* _ASM_RISCV_FENCE_H */

tools/include/asm/barrier.h

+2 −0
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@@ -8,6 +8,8 @@ 
#include "../../arch/arm64/include/asm/barrier.h"

#elif defined(__powerpc__)

#include "../../arch/powerpc/include/asm/barrier.h"

#elif defined(__riscv)

#include "../../arch/riscv/include/asm/barrier.h"

#elif defined(__s390__)

#include "../../arch/s390/include/asm/barrier.h"

#elif defined(__sh__)

tools/include/linux/ring_buffer.h

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ static inline u64 ring_buffer_read_head(struct perf_event_mmap_page *base) 
 * READ_ONCE() + smp_mb() pair.

 */

#if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \

    defined(__ia64__) || defined(__sparc__) && defined(__arch64__)

    defined(__ia64__) || defined(__sparc__) && defined(__arch64__) || defined(__riscv)

	return smp_load_acquire(&base->data_head);

#else

	u64 head = READ_ONCE(base->data_head);