Commit 48055fb8 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/entry' into for-next/core 

* for-next/entry:
  arm64: el2_setup.h: Make __init_el2_fgt labels consistent, again
  arm64: Update comment regarding values in __boot_cpu_mode
  arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1
  arm64: enable PREEMPT_LAZY
parents b5b6910f 80834997

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ config ARM64 
	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS

	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE

	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT

	select ARCH_HAS_PREEMPT_LAZY

	select ARCH_HAS_PTDUMP

	select ARCH_HAS_PTE_DEVMAP

	select ARCH_HAS_PTE_SPECIAL

arch/arm64/include/asm/el2_setup.h

+7 −3
Original line number Diff line number Diff line
@@ -204,19 +204,21 @@ 
	orr	x0, x0, #(1 << 62)



.Lskip_spe_fgt_\@:



.Lset_debug_fgt_\@:

	msr_s	SYS_HDFGRTR_EL2, x0

	msr_s	SYS_HDFGWTR_EL2, x0



	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lskip_debug_fgt_\@

	cbz	x1, .Lskip_sme_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK



.Lskip_debug_fgt_\@:

.Lskip_sme_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4

	cbz	x1, .Lskip_pie_fgt_\@
@@ -237,12 +239,14 @@ 
	/* GCS depends on PIE so we don't check it if PIE is absent */

	mrs_s	x1, SYS_ID_AA64PFR1_EL1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4

	cbz	x1, .Lset_fgt_\@

	cbz	x1, .Lskip_gce_fgt_\@



	/* Disable traps of access to GCS registers at EL0 and EL1 */

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK



.Lskip_gce_fgt_\@:



.Lset_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0

arch/arm64/include/asm/thread_info.h

+9 −7
Original line number Diff line number Diff line
@@ -59,11 +59,12 @@ void arch_setup_new_exec(void); 


#define TIF_SIGPENDING		0	/* signal pending */

#define TIF_NEED_RESCHED	1	/* rescheduling necessary */

#define TIF_NOTIFY_RESUME	2	/* callback before returning to user */

#define TIF_FOREIGN_FPSTATE	3	/* CPU's FP state is not current's */

#define TIF_UPROBE		4	/* uprobe breakpoint or singlestep */

#define TIF_MTE_ASYNC_FAULT	5	/* MTE Asynchronous Tag Check Fault */

#define TIF_NOTIFY_SIGNAL	6	/* signal notifications exist */

#define TIF_NEED_RESCHED_LAZY	2	/* Lazy rescheduling needed */

#define TIF_NOTIFY_RESUME	3	/* callback before returning to user */

#define TIF_FOREIGN_FPSTATE	4	/* CPU's FP state is not current's */

#define TIF_UPROBE		5	/* uprobe breakpoint or singlestep */

#define TIF_MTE_ASYNC_FAULT	6	/* MTE Asynchronous Tag Check Fault */

#define TIF_NOTIFY_SIGNAL	7	/* signal notifications exist */

#define TIF_SYSCALL_TRACE	8	/* syscall trace active */

#define TIF_SYSCALL_AUDIT	9	/* syscall auditing */

#define TIF_SYSCALL_TRACEPOINT	10	/* syscall tracepoint for ftrace */
@@ -85,6 +86,7 @@ void arch_setup_new_exec(void); 


#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)

#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)

#define _TIF_NEED_RESCHED_LAZY	(1 << TIF_NEED_RESCHED_LAZY)

#define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)

#define _TIF_FOREIGN_FPSTATE	(1 << TIF_FOREIGN_FPSTATE)

#define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
@@ -100,10 +102,10 @@ void arch_setup_new_exec(void); 
#define _TIF_NOTIFY_SIGNAL	(1 << TIF_NOTIFY_SIGNAL)

#define _TIF_TSC_SIGSEGV	(1 << TIF_TSC_SIGSEGV)



#define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \

#define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY | \

				 _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \

				 _TIF_UPROBE | _TIF_MTE_ASYNC_FAULT | \

				 _TIF_NOTIFY_SIGNAL)

				 _TIF_NOTIFY_SIGNAL | _TIF_SIGPENDING)



#define _TIF_SYSCALL_WORK	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \

				 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \

arch/arm64/include/asm/virt.h

+2 −1
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ 
 * __boot_cpu_mode records what mode CPUs were booted in.

 * A correctly-implemented bootloader must start all CPUs in the same mode:

 * In this case, both 32bit halves of __boot_cpu_mode will contain the

 * same value (either 0 if booted in EL1, BOOT_CPU_MODE_EL2 if booted in EL2).

 * same value (either BOOT_CPU_MODE_EL1 if booted in EL1, BOOT_CPU_MODE_EL2 if

 * booted in EL2).

 *

 * Should the bootloader fail to do this, the two values will be different.

 * This allows the kernel to flag an error when the secondaries have come up.

arch/arm64/kernel/asm-offsets.c

+2 −0
Original line number Diff line number Diff line
@@ -182,5 +182,7 @@ int main(void) 
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS

  DEFINE(FTRACE_OPS_DIRECT_CALL,	offsetof(struct ftrace_ops, direct_call));

#endif

  DEFINE(PIE_E0_ASM, PIE_E0);

  DEFINE(PIE_E1_ASM, PIE_E1);

  return 0;

}