Commit 480a9e57 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/misc', 'for-next/tlbflush',... 

Merge branches 'for-next/misc', 'for-next/tlbflush', 'for-next/ttbr-macros-cleanup', 'for-next/kselftest', 'for-next/feat_lsui', 'for-next/mpam', 'for-next/hotplug-batched-tlbi', 'for-next/bbml2-fixes', 'for-next/sysreg', 'for-next/generic-entry' and 'for-next/acpi', remote-tracking branches 'arm64/for-next/perf' and 'arm64/for-next/read-once' into for-next/core

* arm64/for-next/perf:
  : Perf updates
  perf/arm-cmn: Fix resource_size_t printk specifier in arm_cmn_init_dtc()
  perf/arm-cmn: Fix incorrect error check for devm_ioremap()
  perf: add NVIDIA Tegra410 C2C PMU
  perf: add NVIDIA Tegra410 CPU Memory Latency PMU
  perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT PMU
  perf/arm_cspmu: nvidia: Add Tegra410 PCIE PMU
  perf/arm_cspmu: Add arm_cspmu_acpi_dev_get
  perf/arm_cspmu: nvidia: Add Tegra410 UCF PMU
  perf/arm_cspmu: nvidia: Rename doc to Tegra241
  perf/arm-cmn: Stop claiming entire iomem region
  arm64: cpufeature: Use pmuv3_implemented() function
  arm64: cpufeature: Make PMUVer and PerfMon unsigned
  KVM: arm64: Read PMUVer as unsigned

* arm64/for-next/read-once:
  : Fixes for __READ_ONCE() with CONFIG_LTO=y
  arm64, compiler-context-analysis: Permit alias analysis through __READ_ONCE() with CONFIG_LTO=y
  arm64: Optimize __READ_ONCE() with CONFIG_LTO=y

* for-next/misc:
  : Miscellaneous cleanups/fixes
  arm64: rsi: use linear-map alias for realm config buffer
  arm64: Kconfig: fix duplicate word in CMDLINE help text
  arm64: mte: Skip TFSR_EL1 checks and barriers in synchronous tag check mode
  arm64/hwcap: Generate the KERNEL_HWCAP_ definitions for the hwcaps
  arm64: kexec: Remove duplicate allocation for trans_pgd
  arm64: mm: Use generic enum pgtable_level
  arm64: scs: Remove redundant save/restore of SCS SP on entry to/from EL0
  arm64: remove ARCH_INLINE_*

* for-next/tlbflush:
  : Refactor the arm64 TLB invalidation API and implementation
  arm64: mm: __ptep_set_access_flags must hint correct TTL
  arm64: mm: Provide level hint for flush_tlb_page()
  arm64: mm: Wrap flush_tlb_page() around __do_flush_tlb_range()
  arm64: mm: More flags for __flush_tlb_range()
  arm64: mm: Refactor __flush_tlb_range() to take flags
  arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid()
  arm64: mm: Simplify __flush_tlb_range_limit_excess()
  arm64: mm: Simplify __TLBI_RANGE_NUM() macro
  arm64: mm: Re-implement the __flush_tlb_range_op macro in C
  arm64: mm: Inline __TLBI_VADDR_RANGE() into __tlbi_range()
  arm64: mm: Push __TLBI_VADDR() into __tlbi_level()
  arm64: mm: Implicitly invalidate user ASID based on TLBI operation
  arm64: mm: Introduce a C wrapper for by-range TLB invalidation
  arm64: mm: Re-implement the __tlbi_level macro as a C function

* for-next/ttbr-macros-cleanup:
  : Cleanups of the TTBR1_* macros
  arm64/mm: Directly use TTBRx_EL1_CnP
  arm64/mm: Directly use TTBRx_EL1_ASID_MASK
  arm64/mm: Describe TTBR1_BADDR_4852_OFFSET

* for-next/kselftest:
  : arm64 kselftest updates
  selftests/arm64: Implement cmpbr_sigill() to hwcap test

* for-next/feat_lsui:
  : Futex support using FEAT_LSUI instructions to avoid toggling PAN
  arm64: armv8_deprecated: Disable swp emulation when FEAT_LSUI present
  arm64: Kconfig: Add support for LSUI
  KVM: arm64: Use CAST instruction for swapping guest descriptor
  arm64: futex: Support futex with FEAT_LSUI
  arm64: futex: Refactor futex atomic operation
  KVM: arm64: kselftest: set_id_regs: Add test for FEAT_LSUI
  KVM: arm64: Expose FEAT_LSUI to guests
  arm64: cpufeature: Add FEAT_LSUI

* for-next/mpam: (40 commits)
  : Expose MPAM to user-space via resctrl:
  :  - Add architecture context-switch and hiding of the feature from KVM.
  :  - Add interface to allow MPAM to be exposed to user-space using resctrl.
  :  - Add errata workaoround for some existing platforms.
  :  - Add documentation for using MPAM and what shape of platforms can use resctrl
  arm64: mpam: Add initial MPAM documentation
  arm_mpam: Quirk CMN-650's CSU NRDY behaviour
  arm_mpam: Add workaround for T241-MPAM-6
  arm_mpam: Add workaround for T241-MPAM-4
  arm_mpam: Add workaround for T241-MPAM-1
  arm_mpam: Add quirk framework
  arm_mpam: resctrl: Call resctrl_init() on platforms that can support resctrl
  arm64: mpam: Select ARCH_HAS_CPU_RESCTRL
  arm_mpam: resctrl: Add empty definitions for assorted resctrl functions
  arm_mpam: resctrl: Update the rmid reallocation limit
  arm_mpam: resctrl: Add resctrl_arch_rmid_read()
  arm_mpam: resctrl: Allow resctrl to allocate monitors
  arm_mpam: resctrl: Add support for csu counters
  arm_mpam: resctrl: Add monitor initialisation and domain boilerplate
  arm_mpam: resctrl: Add kunit test for control format conversions
  arm_mpam: resctrl: Add support for 'MB' resource
  arm_mpam: resctrl: Wait for cacheinfo to be ready
  arm_mpam: resctrl: Add rmid index helpers
  arm_mpam: resctrl: Convert to/from MPAMs fixed-point formats
  arm_mpam: resctrl: Hide CDP emulation behind CONFIG_EXPERT
  ...

* for-next/hotplug-batched-tlbi:
  : arm64/mm: Enable batched TLB flush in unmap_hotplug_range()
  arm64/mm: Reject memory removal that splits a kernel leaf mapping
  arm64/mm: Enable batched TLB flush in unmap_hotplug_range()

* for-next/bbml2-fixes:
  : Fixes for realm guest and BBML2_NOABORT
  arm64: mm: Remove pmd_sect() and pud_sect()
  arm64: mm: Handle invalid large leaf mappings correctly
  arm64: mm: Fix rodata=full block mapping support for realm guests

* for-next/sysreg:
  : arm64 sysreg updates
  arm64/sysreg: Update ID_AA64SMFR0_EL1 description to DDI0601 2025-12
  arm64/sysreg: Update ID_AA64ZFR0_EL1 description to DDI0601 2025-12
  arm64/sysreg: Update ID_AA64FPFR0_EL1 description to DDI0601 2025-12
  arm64/sysreg: Update ID_AA64ISAR2_EL1 description to DDI0601 2025-12
  arm64/sysreg: Update ID_AA64ISAR0_EL1 description to DDI0601 2025-12
  arm64/sysreg: Update SMIDR_EL1 to DDI0601 2025-06

* for-next/generic-entry:
  : More arm64 refactoring towards using the generic entry code
  arm64: Check DAIF (and PMR) at task-switch time
  arm64: entry: Use split preemption logic
  arm64: entry: Use irqentry_{enter_from,exit_to}_kernel_mode()
  arm64: entry: Consistently prefix arm64-specific wrappers
  arm64: entry: Don't preempt with SError or Debug masked
  entry: Split preemption from irqentry_exit_to_kernel_mode()
  entry: Split kernel mode logic from irqentry_{enter,exit}()
  entry: Move irqentry_enter() prototype later
  entry: Remove local_irq_{enable,disable}_exit_to_user()
  entry: Fix stale comment for irqentry_enter()

* for-next/acpi:
  : arm64 ACPI updates
  ACPI: AGDI: fix missing newline in error message
parents 47f06ebb 773b24bc 34e56394 b7d9d2e3 be6e9dee 74cd4e0e e223258e 4ce0a2cc 95a58852 1d37713f 306736fd 8d13386c b178330b

Documentation/arch/arm64/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ ARM64 Architecture 
    memory

    memory-tagging-extension

    mops

    mpam

    perf

    pointer-authentication

    ptdump

Documentation/arch/arm64/mpam.rst

0 → 100644
+72 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0



====

MPAM

====



What is MPAM

============

MPAM (Memory Partitioning and Monitoring) is a feature in the CPUs and memory

system components such as the caches or memory controllers that allow memory

traffic to be labelled, partitioned and monitored.



Traffic is labelled by the CPU, based on the control or monitor group the

current task is assigned to using resctrl.  Partitioning policy can be set

using the schemata file in resctrl, and monitor values read via resctrl.

See Documentation/filesystems/resctrl.rst for more details.



This allows tasks that share memory system resources, such as caches, to be

isolated from each other according to the partitioning policy (so called noisy

neighbours).



Supported Platforms

===================

Use of this feature requires CPU support, support in the memory system

components, and a description from firmware of where the MPAM device controls

are in the MMIO address space. (e.g. the 'MPAM' ACPI table).



The MMIO device that provides MPAM controls/monitors for a memory system

component is called a memory system component. (MSC).



Because the user interface to MPAM is via resctrl, only MPAM features that are

compatible with resctrl can be exposed to user-space.



MSC are considered as a group based on the topology. MSC that correspond with

the L3 cache are considered together, it is not possible to mix MSC between L2

and L3 to 'cover' a resctrl schema.



The supported features are:



* Cache portion bitmap controls (CPOR) on the L2 or L3 caches.  To expose

  CPOR at L2 or L3, every CPU must have a corresponding CPU cache at this

  level that also supports the feature.  Mismatched big/little platforms are

  not supported as resctrl's controls would then also depend on task

  placement.



* Memory bandwidth maximum controls (MBW_MAX) on or after the L3 cache.

  resctrl uses the L3 cache-id to identify where the memory bandwidth

  control is applied. For this reason the platform must have an L3 cache

  with cache-id's supplied by firmware. (It doesn't need to support MPAM.)



  To be exported as the 'MB' schema, the topology of the group of MSC chosen

  must match the topology of the L3 cache so that the cache-id's can be

  repainted. For example: Platforms with Memory bandwidth maximum controls

  on CPU-less NUMA nodes cannot expose the 'MB' schema to resctrl as these

  nodes do not have a corresponding L3 cache. If the memory bandwidth

  control is on the memory rather than the L3 then there must be a single

  global L3 as otherwise it is unknown which L3 the traffic came from. There

  must be no caches between the L3 and the memory so that the two ends of

  the path have equivalent traffic.



  When the MPAM driver finds multiple groups of MSC it can use for the 'MB'

  schema, it prefers the group closest to the L3 cache.



* Cache Storage Usage (CSU) counters can expose the 'llc_occupancy' provided

  there is at least one CSU monitor on each MSC that makes up the L3 group.

  Exposing CSU counters from other caches or devices is not supported.



Reporting Bugs

==============

If you are not seeing the counters or controls you expect please share the

debug messages produced when enabling dynamic debug and booting with:

dyndbg="file mpam_resctrl.c +pl"

Documentation/arch/arm64/silicon-errata.rst

+9 −0
Original line number Diff line number Diff line
@@ -214,6 +214,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | SI L1           | #4311569        | ARM64_ERRATUM_4311569       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | CMN-650         | #3642720        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_843419        |
@@ -247,6 +250,12 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 GICv3/4.x  | T241-FABRIC-4   | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 MPAM       | T241-MPAM-1     | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 MPAM       | T241-MPAM-4     | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 MPAM       | T241-MPAM-6     | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+25 −29
Original line number Diff line number Diff line
@@ -61,32 +61,6 @@ config ARM64 
	select ARCH_HAVE_ELF_PROT

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	select ARCH_HAVE_TRACE_MMIO_ACCESS

	select ARCH_INLINE_READ_LOCK if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION

	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION

	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION

	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION

	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION

	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION

	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION

	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION

	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION

	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION

	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION

	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION

	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION

	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION

	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION

	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION

	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION

	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION

	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION

	select ARCH_KEEP_MEMBLOCK

	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE

	select ARCH_USE_CMPXCHG_LOCKREF
@@ -2016,8 +1990,8 @@ config ARM64_TLB_RANGE 


config ARM64_MPAM

	bool "Enable support for MPAM"

	select ARM64_MPAM_DRIVER if EXPERT	# does nothing yet

	select ACPI_MPAM if ACPI

	select ARM64_MPAM_DRIVER

	select ARCH_HAS_CPU_RESCTRL

	help

	  Memory System Resource Partitioning and Monitoring (MPAM) is an

	  optional extension to the Arm architecture that allows each
@@ -2039,6 +2013,8 @@ config ARM64_MPAM 


	  MPAM is exposed to user-space via the resctrl pseudo filesystem.



	  This option enables the extra context switch code.



endmenu # "ARMv8.4 architectural features"



menu "ARMv8.5 architectural features"
@@ -2215,6 +2191,26 @@ config ARM64_GCS 


endmenu # "ARMv9.4 architectural features"



config AS_HAS_LSUI

	def_bool $(as-instr,.arch_extension lsui)

	help

	  Supported by LLVM 20+ and binutils 2.45+.



menu "ARMv9.6 architectural features"



config ARM64_LSUI

	bool "Support Unprivileged Load Store Instructions (LSUI)"

	default y

	depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN

	help

	  The Unprivileged Load Store Instructions (LSUI) provides

	  variants load/store instructions that access user-space memory

	  from the kernel without clearing PSTATE.PAN bit.



	  This feature is supported by LLVM 20+ and binutils 2.45+.



endmenu # "ARMv9.6 architectural feature"



config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y
@@ -2372,7 +2368,7 @@ config CMDLINE 
	default ""

	help

	  Provide a set of default command-line options at build time by

	  entering them here. As a minimum, you should specify the the

	  entering them here. As a minimum, you should specify the

	  root device (e.g. root=/dev/nfs).



choice

arch/arm64/include/asm/asm-uaccess.h

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#ifdef CONFIG_ARM64_SW_TTBR0_PAN

	.macro	__uaccess_ttbr0_disable, tmp1

	mrs	\tmp1, ttbr1_el1			// swapper_pg_dir

	bic	\tmp1, \tmp1, #TTBR_ASID_MASK

	bic	\tmp1, \tmp1, #TTBRx_EL1_ASID_MASK

	sub	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET	// reserved_pg_dir

	msr	ttbr0_el1, \tmp1			// set reserved TTBR0_EL1

	add	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET