drm/amdgpu/gfx9: properly handle error ints on all pipes (48695573) · Commits · git / linux-net

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+43 −1

Original line number	Diff line number	Diff line
		@@ -5929,17 +5929,59 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
		}
		}

		static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev,
		int me, int pipe)
		{
		/*
		* amdgpu controls only the first MEC. That's why this function only
		* handles the setting of interrupts for this specific MEC. All other
		* pipes' interrupts are set by amdkfd.
		*/
		if (me != 1)
		return 0;

		switch (pipe) {
		case 0:
		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
		case 1:
		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
		case 2:
		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
		case 3:
		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
		default:
		return 0;
		}
		}

		static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
		struct amdgpu_irq_src *source,
		unsigned type,
		enum amdgpu_interrupt_state state)
		{
		u32 cp_int_cntl_reg, cp_int_cntl;
		int i, j;

		switch (state) {
		case AMDGPU_IRQ_STATE_DISABLE:
		case AMDGPU_IRQ_STATE_ENABLE:
		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
		PRIV_REG_INT_ENABLE,
		state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
		/* MECs start at 1 */
		cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);

		if (cp_int_cntl_reg) {
		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
		PRIV_REG_INT_ENABLE,
		state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
		}
		}
		}
		break;
		default:
		break;

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+46 −4

Original line number	Diff line number	Diff line
		@@ -2899,21 +2899,63 @@ static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
		}
		}

		static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev,
		int xcc_id, int me, int pipe)
		{
		/*
		* amdgpu controls only the first MEC. That's why this function only
		* handles the setting of interrupts for this specific MEC. All other
		* pipes' interrupts are set by amdkfd.
		*/
		if (me != 1)
		return 0;

		switch (pipe) {
		case 0:
		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
		case 1:
		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
		case 2:
		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
		case 3:
		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
		default:
		return 0;
		}
		}

		static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
		struct amdgpu_irq_src *source,
		unsigned type,
		enum amdgpu_interrupt_state state)
		{
		int i, num_xcc;
		u32 mec_int_cntl_reg, mec_int_cntl;
		int i, j, k, num_xcc;

		num_xcc = NUM_XCC(adev->gfx.xcc_mask);
		switch (state) {
		case AMDGPU_IRQ_STATE_DISABLE:
		case AMDGPU_IRQ_STATE_ENABLE:
		for (i = 0; i < num_xcc; i++)
		for (i = 0; i < num_xcc; i++) {
		WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
		PRIV_REG_INT_ENABLE,
		state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
		for (j = 0; j < adev->gfx.mec.num_mec; j++) {
		for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
		/* MECs start at 1 */
		mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);

		if (mec_int_cntl_reg) {
		mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);
		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
		PRIV_REG_INT_ENABLE,
		state == AMDGPU_IRQ_STATE_ENABLE ?
		1 : 0);
		WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);
		}
		}
		}
		}
		break;
		default:
		break;