Commit 4897f9b7 authored by Jianbo Liu's avatar Jianbo Liu Committed by Paolo Abeni
Browse files

ethtool: Add support for 200Gbps per lane link modes 



Define 200G, 400G and 800G link modes using 200Gbps per lane.

Signed-off-by: default avatarJianbo Liu <jianbol@nvidia.com>
Reviewed-by: default avatarShahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 39c1202f

drivers/net/phy/phy-core.c

+19 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 */

const char *phy_speed_to_str(int speed)

{

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103,

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121,

		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "

		"If a speed or mode has been added please update phy_speed_to_str "

		"and the PHY settings array.\n");
@@ -169,6 +169,12 @@ static const struct phy_setting settings[] = { 
	PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full		),

	PHY_SETTING( 800000, FULL, 800000baseSR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseVR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseCR4_Full		),

	PHY_SETTING( 800000, FULL, 800000baseKR4_Full		),

	PHY_SETTING( 800000, FULL, 800000baseDR4_Full		),

	PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full		),

	PHY_SETTING( 800000, FULL, 800000baseSR4_Full		),

	PHY_SETTING( 800000, FULL, 800000baseVR4_Full		),

	/* 400G */

	PHY_SETTING( 400000, FULL, 400000baseCR8_Full		),

	PHY_SETTING( 400000, FULL, 400000baseKR8_Full		),
@@ -180,6 +186,12 @@ static const struct phy_setting settings[] = { 
	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),

	PHY_SETTING( 400000, FULL, 400000baseDR4_Full		),

	PHY_SETTING( 400000, FULL, 400000baseSR4_Full		),

	PHY_SETTING( 400000, FULL, 400000baseCR2_Full		),

	PHY_SETTING( 400000, FULL, 400000baseKR2_Full		),

	PHY_SETTING( 400000, FULL, 400000baseDR2_Full		),

	PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full		),

	PHY_SETTING( 400000, FULL, 400000baseSR2_Full		),

	PHY_SETTING( 400000, FULL, 400000baseVR2_Full		),

	/* 200G */

	PHY_SETTING( 200000, FULL, 200000baseCR4_Full		),

	PHY_SETTING( 200000, FULL, 200000baseKR4_Full		),
@@ -191,6 +203,12 @@ static const struct phy_setting settings[] = { 
	PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full	),

	PHY_SETTING( 200000, FULL, 200000baseDR2_Full		),

	PHY_SETTING( 200000, FULL, 200000baseSR2_Full		),

	PHY_SETTING( 200000, FULL, 200000baseCR_Full		),

	PHY_SETTING( 200000, FULL, 200000baseKR_Full		),

	PHY_SETTING( 200000, FULL, 200000baseDR_Full		),

	PHY_SETTING( 200000, FULL, 200000baseDR_2_Full		),

	PHY_SETTING( 200000, FULL, 200000baseSR_Full		),

	PHY_SETTING( 200000, FULL, 200000baseVR_Full		),

	/* 100G */

	PHY_SETTING( 100000, FULL, 100000baseCR4_Full		),

	PHY_SETTING( 100000, FULL, 100000baseKR4_Full		),

include/uapi/linux/ethtool.h

+18 −0
Original line number Diff line number Diff line
@@ -2057,6 +2057,24 @@ enum ethtool_link_mode_bit_indices { 
	ETHTOOL_LINK_MODE_10baseT1S_Half_BIT		 = 100,

	ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT	 = 101,

	ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT		 = 102,

	ETHTOOL_LINK_MODE_200000baseCR_Full_BIT		 = 103,

	ETHTOOL_LINK_MODE_200000baseKR_Full_BIT		 = 104,

	ETHTOOL_LINK_MODE_200000baseDR_Full_BIT		 = 105,

	ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT	 = 106,

	ETHTOOL_LINK_MODE_200000baseSR_Full_BIT		 = 107,

	ETHTOOL_LINK_MODE_200000baseVR_Full_BIT		 = 108,

	ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT	 = 109,

	ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT	 = 110,

	ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT	 = 111,

	ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT	 = 112,

	ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT	 = 113,

	ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT	 = 114,

	ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT	 = 115,

	ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT	 = 116,

	ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT	 = 117,

	ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT	 = 118,

	ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT	 = 119,

	ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT	 = 120,



	/* must be last entry */

	__ETHTOOL_LINK_MODE_MASK_NBITS

net/ethtool/common.c

+42 −0
Original line number Diff line number Diff line
@@ -213,6 +213,24 @@ const char link_mode_names[][ETH_GSTRING_LEN] = { 
	__DEFINE_LINK_MODE_NAME(10, T1S, Half),

	__DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half),

	__DEFINE_LINK_MODE_NAME(10, T1BRR, Full),

	__DEFINE_LINK_MODE_NAME(200000, CR, Full),

	__DEFINE_LINK_MODE_NAME(200000, KR, Full),

	__DEFINE_LINK_MODE_NAME(200000, DR, Full),

	__DEFINE_LINK_MODE_NAME(200000, DR_2, Full),

	__DEFINE_LINK_MODE_NAME(200000, SR, Full),

	__DEFINE_LINK_MODE_NAME(200000, VR, Full),

	__DEFINE_LINK_MODE_NAME(400000, CR2, Full),

	__DEFINE_LINK_MODE_NAME(400000, KR2, Full),

	__DEFINE_LINK_MODE_NAME(400000, DR2, Full),

	__DEFINE_LINK_MODE_NAME(400000, DR2_2, Full),

	__DEFINE_LINK_MODE_NAME(400000, SR2, Full),

	__DEFINE_LINK_MODE_NAME(400000, VR2, Full),

	__DEFINE_LINK_MODE_NAME(800000, CR4, Full),

	__DEFINE_LINK_MODE_NAME(800000, KR4, Full),

	__DEFINE_LINK_MODE_NAME(800000, DR4, Full),

	__DEFINE_LINK_MODE_NAME(800000, DR4_2, Full),

	__DEFINE_LINK_MODE_NAME(800000, SR4, Full),

	__DEFINE_LINK_MODE_NAME(800000, VR4, Full),

};

static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -221,8 +239,11 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); 
#define __LINK_MODE_LANES_CR4		4

#define __LINK_MODE_LANES_CR8		8

#define __LINK_MODE_LANES_DR		1

#define __LINK_MODE_LANES_DR_2		1

#define __LINK_MODE_LANES_DR2		2

#define __LINK_MODE_LANES_DR2_2		2

#define __LINK_MODE_LANES_DR4		4

#define __LINK_MODE_LANES_DR4_2		4

#define __LINK_MODE_LANES_DR8		8

#define __LINK_MODE_LANES_KR		1

#define __LINK_MODE_LANES_KR2		2
@@ -251,6 +272,9 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); 
#define __LINK_MODE_LANES_T1L		1

#define __LINK_MODE_LANES_T1S		1

#define __LINK_MODE_LANES_T1S_P2MP	1

#define __LINK_MODE_LANES_VR		1

#define __LINK_MODE_LANES_VR2		2

#define __LINK_MODE_LANES_VR4		4

#define __LINK_MODE_LANES_VR8		8

#define __LINK_MODE_LANES_DR8_2		8

#define __LINK_MODE_LANES_T1BRR		1
@@ -378,6 +402,24 @@ const struct link_mode_info link_mode_params[] = { 
	__DEFINE_LINK_MODE_PARAMS(10, T1S, Half),

	__DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half),

	__DEFINE_LINK_MODE_PARAMS(10, T1BRR, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, CR, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, KR, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, DR, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, DR_2, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, SR, Full),

	__DEFINE_LINK_MODE_PARAMS(200000, VR, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, CR2, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, KR2, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, DR2, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, DR2_2, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, SR2, Full),

	__DEFINE_LINK_MODE_PARAMS(400000, VR2, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, CR4, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, KR4, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, DR4, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, DR4_2, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, SR4, Full),

	__DEFINE_LINK_MODE_PARAMS(800000, VR4, Full),

};

static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);