Commit 48e70d2a authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe: Move GSC HECI base offsets out of register header 



These offsets are only used to setup the auxiliary device BAR
information and are never used for driver read/write operations.  Move
them to the GSC HECI file where they're actually used.

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-15-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent f52e4e90

drivers/gpu/drm/xe/regs/xe_regs.h

+0 −4
Original line number Diff line number Diff line
@@ -7,10 +7,6 @@ 


#include "regs/xe_reg_defs.h"



#define DG1_GSC_HECI2_BASE			0x00259000

#define PVC_GSC_HECI2_BASE			0x00285000

#define DG2_GSC_HECI2_BASE			0x00374000



#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)

#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)

#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)

drivers/gpu/drm/xe/xe_heci_gsc.c

+4 −0
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ 


#define GSC_BAR_LENGTH  0x00000FFC



#define DG1_GSC_HECI2_BASE			0x259000

#define PVC_GSC_HECI2_BASE			0x285000

#define DG2_GSC_HECI2_BASE			0x374000



static void heci_gsc_irq_mask(struct irq_data *d)

{

	/* generic irq handling */