Commit 48fc4378 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2024-12-25' of... 

Merge tag 'drm-intel-fixes-2024-12-25' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-fixes

- Fix C10 pll programming sequence [cx0_phy] (Suraj Kandpal)
- Fix power gate sequence. [dg1] (Rodrigo Vivi)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z2wKf7tmElKFdnoP@linux
parents 3bce3cc6 20e7c531

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+4 −8
Original line number Diff line number Diff line
@@ -2115,14 +2115,6 @@ static void intel_c10_pll_program(struct intel_display *display, 
		      0, C10_VDR_CTRL_MSGBUS_ACCESS,

		      MB_WRITE_COMMITTED);



	/* Custom width needs to be programmed to 0 for both the phy lanes */

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,

		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,

		      MB_WRITE_COMMITTED);

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),

		      0, C10_VDR_CTRL_UPDATE_CFG,

		      MB_WRITE_COMMITTED);



	/* Program the pll values only for the master lane */

	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

		intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),
@@ -2132,6 +2124,10 @@ static void intel_c10_pll_program(struct intel_display *display, 
	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);



	/* Custom width needs to be programmed to 0 for both the phy lanes */

	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,

		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,

		      MB_WRITE_COMMITTED);

	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),

		      0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,

		      MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/gt/intel_rc6.c

+1 −1
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) 
			GEN9_MEDIA_PG_ENABLE |

			GEN11_MEDIA_SAMPLER_PG_ENABLE;



	if (GRAPHICS_VER(gt->i915) >= 12) {

	if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {

		for (i = 0; i < I915_MAX_VCS; i++)

			if (HAS_ENGINE(gt, _VCS(i)))

				pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |