Commit 491821ce authored by Vaishnav Achath's avatar Vaishnav Achath Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes 

J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX,
DPHY and TI's pixel grabbing wrapper. Add nodes for the same and
keep them disabled by default.

J721E TRM (Section 12.7 Camera Subsystem):
	https://www.ti.com/lit/zip/spruil1



Signed-off-by: default avatarVaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: default avatarJai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20240215085518.552692-7-vaishnav.a@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent f87c8894

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+122 −0
Original line number Diff line number Diff line
@@ -573,6 +573,128 @@ main_timerio_output: pinctrl@104280 { 
		pinctrl-single,function-mask = <0x0000001f>;

	};



	ti_csi2rx0: ticsi2rx@4500000 {

		compatible = "ti,j721e-csi2rx-shim";

		reg = <0x0 0x4500000 0x0 0x1000>;

		ranges;

		#address-cells = <2>;

		#size-cells = <2>;

		dmas = <&main_udmap 0x4940>;

		dma-names = "rx0";

		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";



		cdns_csi2rx0: csi-bridge@4504000 {

			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";

			reg = <0x0 0x4504000 0x0 0x1000>;

			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,

				<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;

			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",

				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";

			phys = <&dphy0>;

			phy-names = "dphy";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				csi0_port0: port@0 {

					reg = <0>;

					status = "disabled";

				};



				csi0_port1: port@1 {

					reg = <1>;

					status = "disabled";

				};



				csi0_port2: port@2 {

					reg = <2>;

					status = "disabled";

				};



				csi0_port3: port@3 {

					reg = <3>;

					status = "disabled";

				};



				csi0_port4: port@4 {

					reg = <4>;

					status = "disabled";

				};

			};

		};

	};



	ti_csi2rx1: ticsi2rx@4510000 {

		compatible = "ti,j721e-csi2rx-shim";

		reg = <0x0 0x4510000 0x0 0x1000>;

		ranges;

		#address-cells = <2>;

		#size-cells = <2>;

		dmas = <&main_udmap 0x4960>;

		dma-names = "rx0";

		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";



		cdns_csi2rx1: csi-bridge@4514000 {

			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";

			reg = <0x0 0x4514000 0x0 0x1000>;

			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,

				 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;

			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",

				      "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";

			phys = <&dphy1>;

			phy-names = "dphy";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				csi1_port0: port@0 {

					reg = <0>;

					status = "disabled";

				};



				csi1_port1: port@1 {

					reg = <1>;

					status = "disabled";

				};



				csi1_port2: port@2 {

					reg = <2>;

					status = "disabled";

				};



				csi1_port3: port@3 {

					reg = <3>;

					status = "disabled";

				};



				csi1_port4: port@4 {

					reg = <4>;

					status = "disabled";

				};

			};

		};

	};



	dphy0: phy@4580000 {

		compatible = "cdns,dphy-rx";

		reg = <0x0 0x4580000 0x0 0x1100>;

		#phy-cells = <0>;

		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";

	};



	dphy1: phy@4590000 {

		compatible = "cdns,dphy-rx";

		reg = <0x0 0x4590000 0x0 0x1100>;

		#phy-cells = <0>;

		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";

	};



	serdes_wiz0: wiz@5000000 {

		compatible = "ti,j721e-wiz-16g";

		#address-cells = <1>;